| Fabrication of high aspect ratio TSV and assembly with fine-pitch low-cost solder microbump for Si interposer technology with high-density interconnects A Yu, JH Lau, SW Ho, A Kumar, WY Hnin, WS Lee, MC Jong, VN Sekhar, ... IEEE transactions on components, packaging and manufacturing technology 1 (9 …, 2011 | 74 | 2011 |
| Wafer level embedding technology for 3D wafer level embedded package A Kumar, X Dingwei, VN Sekhar, S Lim, C Keng, G Sharma, VS Rao, ... 2009 59th electronic components and technology conference, 1289-1296, 2009 | 68 | 2009 |
| Low-loss broadband package platform with surface passivation and TSV for wafer-level packaging of RF-MEMS devices B Chen, VN Sekhar, C Jin, YY Lim, JS Toh, S Fernando, J Sharma IEEE Transactions on Components, Packaging and Manufacturing Technology 3 (9 …, 2013 | 45 | 2013 |
| Embedded wafer level packages with laterally placed and vertically stacked thin dies G Sharma, VS Rao, A Kumar, N Su, LY Ying, KC Houe, S Lim, VN Sekhar, ... 2009 59th Electronic Components and Technology Conference, 1537-1543, 2009 | 42 | 2009 |
| Non-destructive testing of a high dense small dimension through silicon via (TSV) array structures by using 3D X-ray computed tomography method (CT scan) VN Sekhar, S Neo, LH Yu, AD Trigg, CC Kuo 2010 12th Electronics Packaging Technology Conference, 462-466, 2010 | 39 | 2010 |
| Antenna-in-package design based on wafer-level packaging with through silicon via technology C Jin, VN Sekhar, X Bao, B Chen, B Zheng, R Li IEEE Transactions on Components, Packaging and Manufacturing Technology 3 (9 …, 2013 | 32 | 2013 |
| Nanoindentation in Materials Science J Nemecek BoD–Books on Demand, 2012 | 29 | 2012 |
| Development of package-on-package using embedded wafer-level package approach SC Chong, DHS Wee, VS Rao, NS Vasarla IEEE Transactions on Components, Packaging and Manufacturing Technology 3 …, 2013 | 27 | 2013 |
| Process and reliability assessment of 200μm-thin embedded wafer level packages (EMWLPs) HJ Kim, SC Chong, DSW Ho, EWY Yong, CH Khong, CWL Teo, ... 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 78-83, 2011 | 27 | 2011 |
| 6um pitch high density Cu-Cu bonding for 3D IC stacking L Xie, S Wickramanayaka, SC Chong, VN Sekhar, D Ismeal, YL Ye 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2126-2133, 2016 | 24 | 2016 |
| Impact of packaging design on reliability of large die Cu/low-κ (BD) interconnect TC Chai, X Zhang, HY Li, VN Sekhar, WY Hnin, ML Thew, OK Navas, ... 2008 58th Electronic Components and Technology Conference, 38-45, 2008 | 21 | 2008 |
| Panel warpage of fan-out panel-level packaging using RDL-first technology FX Che, K Yamamoto, VS Rao, VN Sekhar IEEE Transactions on Components, Packaging and Manufacturing Technology 10 …, 2019 | 20 | 2019 |
| Influence of thickness on nanomechanical behavior of Black Diamond™ low dielectric thin films for interconnect and packaging applications VN Sekhar, TC Chai, S Balakumar, L Shen, SK Sinha, AAO Tay, SW Yoon Journal of Materials Science: Materials in Electronics 20, 74-86, 2009 | 15 | 2009 |
| Effect of wafer back grinding on the mechanical behavior of multilayered low-k for 3D-stack packaging applications VN Sekhar, L Shen, A Kumar, TC Chai, WSV Lee, WXL Sandy, X Zhang, ... 2008 58th Electronic Components and Technology Conference, 1517-1524, 2008 | 13 | 2008 |
| Study on warpage of fan-out panel level packaging (FO-PLP) using Gen-3 panel FX Che, K Yamamoto, VS Rao, VN Sekhar 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 842-849, 2019 | 12 | 2019 |
| High-throughput Thermal Compression Bonding of 20 um Pitch Cu Pillar with Gas Pressure Bonder for 3D IC Stacking L Xie, S Wickramanayaka, SC Chong, VN Sekhar, DI Cereno 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 108-114, 2016 | 12 | 2016 |
| Study on the effect of wafer back grinding process on nanomechanical behavior of multilayered low-k stack VN Sekhar, L Shen, A Kumar, TC Chai, X Zhang, CS Premchandran, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 2 (1 …, 2011 | 12 | 2011 |
| Development of a Cu/Low- Stack Die Fine Pitch Ball Grid Array (FBGA) Package for System in Package Applications X Zhang, JH Lau, CS Premachandran, SC Chong, LC Wai, V Lee, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (3 …, 2011 | 12 | 2011 |
| Fractal analysis of intermetallic compounds in Sn–Ag, Sn–Ag–Bi, and Sn–Ag–Cu diffusion couples R Jayaganthan, K Mohankumar, VN Sekhar, AAO Tay, V Kripesh Materials Letters 60 (8), 1089-1094, 2006 | 12 | 2006 |
| Underfill selection, characterization, and reliability study for fine-pitch, large die Cu/low-k flip chip package YY Ong, SW Ho, VN Sekhar, X Ong, J Ong, X Zhang, K Vaidyanathan, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (3 …, 2011 | 11 | 2011 |
