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vempati Srinivasa rao
vempati Srinivasa rao
Institute of Microelectronics
Verified email at ime.a-star.edu.sg
Title
Cited by
Cited by
Year
Development of 3-D silicon module with TSV for system in packaging
N Khan, VS Rao, S Lim, HS We, V Lee, X Zhang, EB Liao, R Nagarajan, ...
IEEE Transactions on Components and Packaging Technologies 33 (1), 3-9, 2010
1832010
Development of through silicon via (TSV) interposer technology for large die (21 21mm) fine-pitch Cu/low-k FCBGA package
X Zhang, TC Chai, JH Lau, CS Selvanayagam, K Biswas, S Liu, D Pinjala, ...
2009 59th Electronic components and technology conference, 305-312, 2009
1252009
Electromigration in flip chip solder joints having a thick Cu column bump and a shallow solder interconnect
JW Nah, JO Suh, KN Tu, SW Yoon, VS Rao, V Kripesh, F Hua
Journal of applied physics 100 (12), 123513, 2006
1152006
Development of high density fan out wafer level package (HD FOWLP) with multi-layer fine pitch RDL for mobile applications
VS Rao, CT Chong, D Ho, DM Zhi, CS Choong, LPS Sharon, D Ismael, ...
2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 1522-1529, 2016
992016
TSV interposer fabrication for 3D IC packaging
VS Rao, HS Wee, LWS Vincent, LH Yu, L Ebin, R Nagarajan, CT Chong, ...
2009 11th Electronics Packaging Technology Conference, 431-437, 2009
812009
Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects
SR Vempati, N Su, CH Khong, YY Lim, K Vaidyanathan, JH Lau, BP Liew, ...
2009 59th Electronic Components and Technology Conference, 980-987, 2009
512009
A novel method to predict die shift during compression molding in embedded wafer level package
CH Khong, A Kumar, X Zhang, G Sharma, SR Vempati, K Vaidyanathan, ...
2009 59th Electronic Components and Technology Conference, 535-541, 2009
502009
A thick photoresist process for advanced wafer level packaging applications using JSR THB-151N negative tone UV photoresist
VS Rao, V Kripesh, SW Yoon, AAO Tay
Journal of Micromechanics and Microengineering 16 (9), 1841, 2006
452006
Copper interconnections for high performance and fine pitch flip chip digital applications and ultra-miniaturized RF module applications
RR Tummala, PM Raj, A Aggarwal, G Mehrotra, SW Koh, S Bansal, ...
56th Electronic Components and Technology Conference 2006, 10 pp., 2006
412006
Electromigration study of 50 m pitch micro solder bumps using four-point Kelvin structure
DQ Yu, TC Chai, ML Thew, YY Ong, VS Rao, LC Wai, JH Lau
2009 59th Electronic Components and Technology Conference, 930-935, 2009
342009
Process development and reliability of microbumps
SPS Lim, VS Rao, WY Hnin, WL Ching, V Kripesh, C Lee, J Lau, J Milla, ...
IEEE transactions on Components and Packaging Technologies 33 (4), 747-753, 2010
322010
Development of coaxial shield via in silicon carrier for high frequency application
SW Ho, VS Rao, OKN Khan, SU Yoon, V Kripesh
2006 8th Electronics Packaging Technology Conference, 825-830, 2006
302006
Development of package-on-package using embedded wafer-level package approach
SC Chong, DHS Wee, VS Rao, NS Vasarla
IEEE Transactions on Components, Packaging and Manufacturing Technology 3…, 2013
252013
Process and reliability assessment of 200μm-thin embedded wafer level packages (EMWLPs)
HJ Kim, SC Chong, DSW Ho, EWY Yong, CH Khong, CWL Teo, ...
2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 78-83, 2011
252011
Bed of nails-100 microns pitch wafer level interconnections process
VS Rao, AAO Tay, V Kripesh, CT Lim, SW Yoon
Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004…, 2004
242004
Process and reliability of large fan-out wafer level package based package-on-package
VS Rao, CT Chong, D Ho, DM Zhi, CS Choong, SL PS, D Ismael, ...
2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 615-622, 2017
232017
Process challenges and development of eWLP
SC Chong, CH Khong, KLC Sing, DHS Wee, CTW Liang, VLW Sheng, ...
2010 12th Electronics Packaging Technology Conference, 527-531, 2010
232010
Application of piezoresistive stress sensor in wafer bumping and drop impact test of embedded ultrathin device
X Zhang, R Rajoo, CS Selvanayagam, A Kumar, VS Rao, N Khan, ...
IEEE Transactions on Components, Packaging and Manufacturing Technology 2 (6…, 2012
212012
Assembly and reliability of micro-bumped chips with through-silicon vias (TSV) interposer
YY Ong, TC Chai, D Yu, ML Thew, E Myo, LC Wai, MC Jong, VS Rao, ...
2009 11th Electronics Packaging Technology Conference, 452-458, 2009
212009
Die package and a method for manufacturing the die package
V Kripesh, NKO Kalandar, SR Vempati, A Kumar, SW Ho, YLS Lim, ...
US Patent App. 12/673,503, 2011
202011
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