| High-temperature lead-free solder alternatives V Chidambaram, J Hattel, J Hald Microelectronic Engineering 88 (6), 981-989, 2011 | 211 | 2011 |
| Development of Au–Ge based candidate alloys as an alternative to high-lead content solders V Chidambaram, J Hald, J Hattel Journal of alloys and compounds 490 (1-2), 170-179, 2010 | 142 | 2010 |
| Design of lead-free candidate alloys for high-temperature soldering based on the Au–Sn system V Chidambaram, J Hattel, J Hald Materials & design 31 (10), 4638-4645, 2010 | 101 | 2010 |
| Reliability of Au-Ge and Au-Si eutectic solder alloys for high-temperature electronics V Chidambaram, HB Yeung, G Shan Journal of electronic materials 41, 2107-2117, 2012 | 65 | 2012 |
| Titanium-based getter solution for wafer-level MEMS vacuum packaging V Chidambaram, X Ling, C Bangtao Journal of electronic materials 42, 485-491, 2013 | 51 | 2013 |
| Development of gold based solder candidates for flip chip assembly V Chidambaram, J Hald, J Hattel Microelectronics Reliability 49 (3), 323-330, 2009 | 37 | 2009 |
| A corrosion investigation of solder candidates for high-temperature applications V Chidambaram, J Hald, R Ambat, J Hattel Jom 61, 59-65, 2009 | 35 | 2009 |
| Dielectric materials characterization for hybrid bonding V Chidambaram, P Lianto, X Wang, G See, N Wiswell, M Kawano 2021 IEEE 71st electronic components and technology conference (ECTC), 426-431, 2021 | 29 | 2021 |
| Comprehensive study on Chip to wafer hybrid bonding process for fine pitch high density heterogeneous applications SPS Lim, SC Chong, V Chidambaram 2021 IEEE 71st electronic components and technology conference (ECTC), 438-444, 2021 | 22 | 2021 |
| Cyanate ester-based encapsulation material for high-temperature applications V Chidambaram, EPJ Rong, GC Lip, RMW Daniel Journal of electronic materials 42, 2803-2812, 2013 | 19 | 2013 |
| Au-In-based hermetic sealing for MEMS packaging for down-hole application V Chidambaram, C Bangtao, GC Lip, D Rhee Min Woo Journal of electronic materials 43, 2498-2509, 2014 | 17 | 2014 |
| Active through-silicon interposer based 2.5 D IC design, fabrication, assembly and test J Jayabalan, V Chidambaram, SLP Siang, W Xiangyu, JM Chinq, ... 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 587-593, 2019 | 15 | 2019 |
| High temperature endurable hermetic sealing material selection and reliability comparison for IR gas sensor module packaging KY Au, DM Zhi, V Chidambaram, B Lin, K Piotr, C KaiLiang 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 1-5, 2016 | 14 | 2016 |
| Development of metallic hermetic sealing for MEMS packaging for harsh environment applications V Chidambaram, HB Yeung, G Shan Journal of electronic materials 41, 2256-2266, 2012 | 12 | 2012 |
| High reliability gold based solder alloys for micro-electronics packaging for high temperature applications V Chidambaram, HB Yeung, G Shan 2012 19th IEEE International Symposium on the Physical and Failure Analysis …, 2012 | 12 | 2012 |
| Heterogeneous system level integration using active Si interposer V Chidambaram, SLP Siang, W Xiangyu, VN Sekhar, S Bhattacharya IEEE Journal of the Electron Devices Society 7, 1209-1216, 2019 | 9 | 2019 |
| A feasibility study of lead free solders for level 1 packaging applications V Chidambaram, J Hald, J Hattel Journal of microelectronics and electronic packaging 6 (1), 75-82, 2009 | 9 | 2009 |
| High-temperature endurable encapsulation material V Chidambaram, HB Yeung, CY Sing, DRM Woo 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC), 61-66, 2012 | 8 | 2012 |
| Development of CMOS compatible bonding material and process for wafer level mems packaging application under harsh environment V Chidambaram, HB Yeung, G Shan 2012 International Conference on Solid-State and Integrated Circuit (ICSIC 2012), 2012 | 8 | 2012 |
| Wafer Level Fine-Pitch Hybrid Bonding: Challenges and Remedies V Chidambaram, YW Leong, Q Ren 2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC), 459-463, 2020 | 7 | 2020 |
Jesper HattelProfessor, Mechanical Engineering, DTUVerified email at mek.dtu.dk
