Paulo Francisco Butzen
Paulo Francisco Butzen
Professor at Federal University of Rio Grande Sul
Verified email at ufrgs.br
Title
Cited by
Cited by
Year
Leakage current in sub-micrometer cmos gates
PF Butzen, RP Ribas
Universidade Federal do Rio Grande do Sul, 1-28, 2006
632006
An array-based test circuit for fully automated gate dielectric breakdown characterization
J Keane, S Venkatraman, PF Butzen, CH Kim
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (5), 787 …, 2011
392011
BTI, HCI and TDDB aging impact in flip–flops
C Nunes, PF Butzen, AI Reis, RP Ribas
Microelectronics Reliability 53 (9-11), 1355-1359, 2013
342013
Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits
PF Butzen, LS da Rosa Jr, EJD Chiappetta Filho, AI Reis, RP Ribas
Microelectronics Journal 41 (4), 247-255, 2010
202010
Transistor network restructuring against NBTI degradation
PF Butzen, V Dal Bem, AI Reis, RP Ribas
Microelectronics Reliability 50 (9-11), 1298-1303, 2010
192010
Design of CMOS logic gates with enhanced robustness against aging degradation
PF Butzen, V Dal Bem, AI Reis, RP Ribas
Microelectronics Reliability 52 (9-10), 1822-1826, 2012
142012
Desenvolvendo o Raciocínio Lógico no Ensino Médio: uma proposta utilizando a ferramenta Scratch
FP Mota, NFA Ribeiro, L Emmendorfer, P Butzen, KS Machado, ...
Brazilian Symposium on Computers in Education (Simpósio Brasileiro de …, 2014
122014
Impact and optimization of lithography-aware regular layout in digital circuit design
V Dal Bem, P Butzen, FS Marranghello, AI Reis, RP Ribas
2011 IEEE 29th International Conference on Computer Design (ICCD), 279-284, 2011
112011
LeomarS. daRosaJr, ErasmoJ. D. ChiappettaFilho, Andre I. Reis., RenatoP. Ribas,―Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled …
PF Butzen
Microelectronics Journal 4, 247-255, 2010
8*2010
PVT variability analysis of FinFET and CMOS XOR circuits at 16nm
FGRG da Silva, PF Butzen, C Meinhardt
2016 IEEE International Conference on Electronics, Circuits and Systems …, 2016
72016
BTI and HCI first-order aging estimation for early use in standard cell technology mapping
PF Butzen, V Dal Bem, AI Reis, RP Ribas
Microelectronics Reliability 53 (9-11), 1360-1364, 2013
62013
A Tool to Evaluate Stuck-Open Faults in CMOS Logic Gates
AL Zimpeck, C Meinhardt, PF Butzen
Simpósio Sul de Microeletrônica (SIM), 2013
62013
Modeling and estimating leakage current in series-parallel cmos networks
PF Butzen, AI Reis, CH Kim, RP Ribas
Proceedings of the 17th ACM Great Lakes symposium on VLSI, 269-274, 2007
62007
Leakage current modeling in Sub-micrometer CMOS complex gates
PF Butzen
62007
A methodology to evaluate the aging impact on flip-flops performance
C Nunes, PF Butzen, AI Reis, RP Ribas
2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013
52013
Probabilistic Method for Reliability Estimation of SP-Networks considering Single Event Transient Faults
R Schvittz, DT Franco, LS Rosa, PF Butzen
2018 25th IEEE International Conference on Electronics, Circuits and Systems …, 2018
42018
Análise do comportamento de portas lógicas CMOS com falhas Stuck-On em nanotecnologias
AL Zimpeck, C Meinhardt, PF Butzen
42014
A probabilistic model for stuck-on faults in combinational logic gates
RB Schivittz, DT Franco, C Meinhardt, PF Butzen
2016 17th Latin-American Test Symposium (LATS), 39-44, 2016
32016
An incremental timing-driven flow using quadratic formulation for detailed placement
G Flach, J Monteiro, M Fogaça, J Puget, P Butzen, M Johann, R Reis
2015 IFIP/IEEE International Conference on Very Large Scale Integration …, 2015
32015
A new methodology to evaluate the Holding Time in CMOS Logic Gates with Stuck-Open Fault
AL Zimpeck, C Meinhardt, PF Butezen
Chip in Curitiba-SForum, 2013
32013
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Articles 1–20