| Novel systolization of subquadratic space complexity multipliers based on toeplitz matrix–vector product approach JS Pan, CY Lee, A Sghaier, M Zeghid, J Xie IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (7 …, 2019 | 145 | 2019 |
| FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures J Xie, J He, G Tan Microelectronics journal 41 (6), 365-370, 2010 | 57 | 2010 |
| Low Latency Systolic Montgomery Multiplier for Finite Field Based on Pentanomials J Xie, J jun He, PK Meher IEEE transactions on very large scale integration (VLSI) systems 21 (2), 385-389, 2012 | 56 | 2012 |
| Special session: The recent advance in hardware implementation of post-quantum cryptography J Xie, K Basu, K Gaj, U Guin 2020 IEEE 38th VLSI Test Symposium (VTS), 1-10, 2020 | 41 | 2020 |
| Hardware-efficient realization of prime-length DCT based on distributed arithmetic J Xie, PK Meher, J He IEEE Transactions on Computers 62 (6), 1170-1178, 2012 | 40 | 2012 |
| Low-Complexity Multiplier for Based on All-One Polynomials J Xie, PK Meher, J He IEEE transactions on very large scale integration (VLSI) systems 21 (1), 168-173, 2012 | 38 | 2012 |
| Low-Latency High-Throughput Systolic Multipliers Over for NIST Recommended Pentanomials J Xie, PK Meher, ZH Mao IEEE Transactions on Circuits and Systems I: Regular Papers 62 (3), 881-890, 2015 | 28 | 2015 |
| High-throughput finite field multipliers using redundant basis for FPGA and ASIC implementations J Xie, PK Meher, ZH Mao IEEE Transactions on Circuits and Systems I: Regular Papers 62 (1), 110-119, 2014 | 28 | 2014 |
| Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over Based on NIST Polynomials J Xie, PK Meher, M Sun, Y Li, B Zeng, ZH Mao IEEE Transactions on Circuits and Systems I: Regular Papers 64 (7), 1815-1825, 2017 | 27 | 2017 |
| Error detection reliable architectures of Camellia block cipher applicable to different variants of its substitution boxes MM Kermani, R Azarderakhsh, J Xie 2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), 1-6, 2016 | 27 | 2016 |
| Lightweight hardware implementation of binary ring-LWE PQC accelerator BJ Lucas, A Alwan, M Murzello, Y Tu, P He, AJ Schwartz, D Guevara, ... IEEE Computer Architecture Letters 21 (1), 17-20, 2022 | 23 | 2022 |
| Certificateless signature schemes in Industrial Internet of Things: A comparative survey S Hussain, SS Ullah, I Ali, J Xie, VN Inukollu Computer Communications 181, 116-131, 2022 | 23 | 2022 |
| Low-latency area-delay-efficient systolic multiplier over GF(2m) for a wider class of trinomials using parallel register sharing J Xie, PK Meher, J He 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 89-92, 2012 | 22 | 2012 |
| Novel low-complexity polynomial multiplication over hybrid fields for efficient implementation of binary ring-LWE post-quantum cryptography P He, U Guin, J Xie IEEE Journal on Emerging and Selected Topics in Circuits and Systems 11 (2 …, 2021 | 21 | 2021 |
| Efficient implementation of finite field arithmetic for binary ring-LWE post-quantum cryptography through a novel lookup-table-like method J Xie, P He, W Wen 2021 58th ACM/IEEE Design Automation Conference (DAC), 1279-1284, 2021 | 20 | 2021 |
| Efficient Hardware Implementation of Finite Field Arithmetic for Binary Ring-LWE Based Post-Quantum Cryptography J Xie, P He, X Wang, JL Imana IEEE Transactions on Emerging Topics in Computing 10 (2), 1222-1228, 2021 | 20 | 2021 |
| Efficient hardware arithmetic for inverted binary ring-lwe based post-quantum cryptography JL Imana, P He, T Bao, Y Tu, J Xie IEEE Transactions on Circuits and Systems I: Regular Papers 69 (8), 3297-3307, 2022 | 19 | 2022 |
| FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over and Their Applications in Trinomial Multipliers P Chen, SN Basha, M Mozaffari-Kermani, R Azarderakhsh, J Xie IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (2), 725-734, 2016 | 18 | 2016 |
| Digit-serial versatile multiplier based on a novel block recombination of the modified overlap-free Karatsuba algorithm CY Lee, J Xie IEEE Transactions on Circuits and Systems I: Regular Papers 66 (1), 203-214, 2018 | 17 | 2018 |
| Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over Based on Reordered Normal Basis J Xie, CY Lee, PK Meher, ZH Mao IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (9 …, 2019 | 15 | 2019 |
