| A knowledge-based system for designing testable VLSI chips MS Abadir, MA Breuer IEEE Design & Test of computers 2 (4), 56-68, 1985 | 314 | 1985 |
| Logic design verification via test generation MS Abadir, J Ferguson, TE Kirkland IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1988 | 266 | 1988 |
| Functional testing of semiconductor random access memories MS Abadir, HK Reghbati ACM Computing Surveys (CSUR) 15 (3), 175-198, 1983 | 242 | 1983 |
| Challenges and trends in modern SoC design verification W Chen, S Ray, J Bhadra, M Abadir, LC Wang IEEE Design & Test 34 (5), 7-22, 2017 | 120 | 2017 |
| Post-verification debugging of hierarchical designs MF Ali, S Safarpour, A Veneris, MS Abadir, R Drechsler ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 106 | 2005 |
| On correlating structural tests with functional tests for speed binning of high performance design J Zeng, MS Abadir, G Vandling, LC Wang, S Karako, JA Abraham Fifth International Workshop on Microprocessor Test and Verification (MTV'04 …, 2004 | 104 | 2004 |
| A survey of hybrid techniques for functional verification J Bhadra, MS Abadir, LC Wang, S Ray IEEE Design & Test of Computers 24 (02), 112-122, 2007 | 97 | 2007 |
| Automatic Test Knowledge Extraction from VHDL (ATKET). P Vishakantaiah, JA Abraham, M Abadir DAC, 273-278, 1992 | 85 | 1992 |
| Debugging sequential circuits using Boolean satisfiability MF Ali, A Veneris, S Safarpour, M Abadir, R Drechsler, A Smith Fifth International Workshop on Microprocessor Test and Verification (MTV'04 …, 2004 | 82 | 2004 |
| Formal verification of content addressable memories using symbolic trajectory evaluation M Pandey, R Raimi, RE Bryant, MS Abadir Proceedings of the 34th annual Design Automation Conference, 167-172, 1997 | 79 | 1997 |
| Fault equivalence and diagnostic test generation using ATPG A Veneris, R Chang, MS Abadir, M Amiri 2004 IEEE International Symposium on Circuits and Systems (ISCAS) 5, V-V, 2004 | 77 | 2004 |
| A genetic approach to automatic bias generation for biased random instruction generation M Bose, J Shin, EM Rudnick, T Dukes, M Abadir Proceedings of the 2001 Congress on Evolutionary Computation (IEEE Cat. No …, 2001 | 67 | 2001 |
| IBDDs: An efficient functional representation for digital circuits J Jain, M Abadir, J Bitner, DS Fussell, JA Abraham Proceedings The European Conference on Design Automation, 440,441,442,443 …, 1992 | 66 | 1992 |
| Automatic generation of assertions for formal verification of powerpc microprocessor arrays using symbolic trajectory evaluation LC Wang, MS Abadir, N Krishnamurthy Proceedings of the 35th annual Design Automation Conference, 534-537, 1998 | 59 | 1998 |
| Test schedules for VLSI circuits having built-in test hardware Abadir, Breuer IEEE Transactions on Computers 100 (4), 361-367, 1986 | 59 | 1986 |
| Delay defect diagnosis based upon a statistical timing model–the first step A Krstic, LC Wang, KT Cheng, JJ Liou, MS Abadir IEE Proceedings-Computers and Digital Techniques 150 (5), 346-354, 2003 | 57 | 2003 |
| Indexed BDDs: Algorithmic advances in techniques to represent and verify Boolean functions J Jain, J Bitner, MS Abadir, JA Abraham, DS Fussell IEEE Transactions on Computers 46 (11), 1230-1245, 1997 | 57 | 1997 |
| Analytical models for leakage power estimation of memory array structures M Mamidipaka, K Khouri, N Dutt, M Abadir Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware …, 2004 | 52 | 2004 |
| Constructing optimal test schedules for VLSI circuits having built-in test hardware MS Abadir, MA Breuer Proc. Int. Symp. Fault-Tolerant Comput, 165-170, 1985 | 52 | 1985 |
| Coverage metrics for verification of concurrent SystemC designs using mutation testing A Sen, MS Abadir 2010 IEEE International High Level Design Validation and Test Workshop …, 2010 | 51 | 2010 |
