Seznec Andre
Seznec Andre
INRIA/IRISA
Verified email at inria.fr - Homepage
Title
Cited by
Cited by
Year
A case for two-way skewed-associative caches
A Seznec
ACM SIGARCH computer architecture news 21 (2), 169-178, 1993
4191993
Design tradeoffs for the Alpha EV8 conditional branch predictor
A Seznec, S Felix, V Krishnan, Y Sazeides
ACM SIGARCH Computer Architecture News 30 (2), 295-306, 2002
2632002
Trading conflict and capacity aliasing in conditional branch predictors
P Michaud, A Seznec, R Uhlig
Proceedings of the 24th annual international symposium on Computer …, 1997
2621997
A case for (partially) TAgged GEometric history length branch prediction
A Seznec, P Michaud
The Journal of Instruction-Level Parallelism 8, 23, 2006
2392006
Decoupled sectored caches: conciliating low tag implementation cost
A Seznec
Proceedings of the 21st annual international symposium on Computer …, 1994
1571994
Analysis of the o-geometric history length branch predictor
A Seznec
32nd International Symposium on Computer Architecture (ISCA'05), 394-405, 2005
1552005
Performance implications of single thread migration on a chip multi-core
T Constantinou, Y Sazeides, P Michaud, D Fetis, A Seznec
ACM SIGARCH Computer Architecture News 33 (4), 80-91, 2005
1522005
A 256 kbits l-tage branch predictor
A Seznec
Journal of Instruction-Level Parallelism (JILP) Special Issue: The Second …, 2007
1492007
Multiple-block ahead branch predictors
A Seznec, S Jourdan, P Sainrat, P Michaud
ACM SIGPLAN Notices 31 (9), 116-127, 1996
1491996
Improving cache behavior of dynamically allocated data structures
DN Truong, F Bodin, A Seznec
Proceedings. 1998 International Conference on Parallel Architectures and …, 1998
1481998
Zero-Content augmented caches
J Dusser, T Piquet, A Seznec
INRIA, 2008
1462008
Choosing representative slices of program execution for microarchitecture simulations: A preliminary application to the data stream
T Lafage, A Seznec
Workload characterization of emerging computer applications, 145-163, 2001
1422001
Data-flow prescheduling for large instruction windows in out-of-order processors
P Michaud, A Seznec
Proceedings HPCA Seventh International Symposium on High-Performance …, 2001
1362001
Tarantula: A vector extension to the alpha architecture
R Espasa, F Ardanaz, J Emer, S Felix, J Gago, R Gramunt, I Hernandez, ...
Proceedings 29th Annual International Symposium on Computer Architecture …, 2002
1352002
A new case for the tage branch predictor
A Seznec
Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011
1192011
Practical and secure pcm systems by online detection of malicious write streams
MK Qureshi, A Seznec, LA Lastras, MM Franceschini
2011 IEEE 17th International symposium on high performance computer …, 2011
1092011
Performance upper bound analysis and optimization of SGEMM on Fermi and Kepler GPUs
J Lai, A Seznec
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation …, 2013
1032013
Skewed-associative caches
A Seznec, F Bodin
International Conference on Parallel Architectures and Languages Europe, 305-316, 1993
1011993
The strict avalanche criterion randomness test
JCH Castro, JM Sierra, A Seznec, A Izquierdo, A Ribagorda
Mathematics and Computers in Simulation 68 (1), 1-7, 2005
872005
A 64-kbytes ittage indirect branch predictor
A Seznec
JWAC-2: Championship Branch Prediction, 2011
832011
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