| At-speed on-chip diagnosis of board-level interconnect faults A Jutman Formal Proc. of 9th European Test Symposium, France, 2-7, 2004 | 68 | 2004 |
| Parallel X-fault simulation with critical path tracing technique R Ubar, S Devadze, J Raik, A Jutman Proceedings of the Conference on Design, Automation and Test in Europe, 879-884, 2010 | 45 | 2010 |
| A suite of IEEE 1687 benchmark networks A Tšertov, A Jutman, S Devadze, MS Reorda, E Larsson, FG Zadegan, ... 2016 IEEE International Test Conference (ITC), 1-10, 2016 | 42 | 2016 |
| SSBDDs: Advantageous model and efficient algorithms for digital circuit modeling, simulation & test A Jutman, J Raik, R Ubar Proc. of 5th International Workshop on Boolean Problems (IWSBP'02), 19-20, 2002 | 40 | 2002 |
| Effective scalable IEEE 1687 instrumentation network for fault management A Jutman, S Devadze, K Shibin IEEE Design & Test 30 (5), 26-35, 2013 | 31 | 2013 |
| Design, verification, and application of IEEE 1687 FG Zadegan, E Larsson, A Jutman, S Devadze, R Krenz-Baath 2014 IEEE 23rd Asian Test Symposium, 93-100, 2014 | 29 | 2014 |
| Turbo Tester–diagnostic package for research and training M Aarna, E Ivask, A Jutman, E Orasson, J Raik, R Ubar, V Vislogubov, ... Радиоэлектроника и информатика, 69-73, 2003 | 29 | 2003 |
| Fast extended test access via JTAG and FPGAs S Devadze, A Jutman, I Aleksejev, R Ubar 2009 International Test Conference, 1-7, 2009 | 26 | 2009 |
| Structurally synthesized binary decision diagrams A Jutman, A Peder, J Raik, M Tombak, R Ubar 6th International Workshop on Boolean Problems, 271-278, 2004 | 25 | 2004 |
| FPGA-based synthetic instrumentation for board test I Aleksejev, A Jutman, S Devadze, S Odintsov, T Wenzel 2012 IEEE International Test Conference, 1-10, 2012 | 24 | 2012 |
| Structural fault collapsing by superposition of BDDs for test generation in digital circuits R Ubar, D Mironov, J Raik, A Jutman 2010 11th International Symposium on Quality Electronic Design (ISQED), 250-257, 2010 | 24 | 2010 |
| Ultra fast parallel fault analysis on structurally synthesized bdds R Ubar, S Devadze, J Raik, A Jutman 12th IEEE European Test Symposium (ETS'07), 131-136, 2007 | 23 | 2007 |
| Design error diagnosis in digital circuits with stuck-at fault model A Jutman, R Ubar Microelectronics Reliability 40 (2), 307-320, 2000 | 22 | 2000 |
| Off-line testing of delay faults in NoC interconnects T Bengtsson, A Jutman, S Kumar, R Ubar, Z Peng 9th EUROMICRO Conference on Digital System Design (DSD'06), 677-680, 2006 | 19 | 2006 |
| DefSim: A remote laboratory for studying physical defects in CMOS digital circuits WA Pleskacz, V Stopjakova, T Borejko, A Jutman IEEE Transactions on Industrial Electronics 55 (6), 2405-2415, 2008 | 17 | 2008 |
| Asynchronous fault detection in IEEE P1687 instrument network K Shibin, S Devadze, A Jutman IEEE North Atlantic Test Workshop (NATW’2014), 2014 | 16 | 2014 |
| Diagnostic modelling of digital systems with multi-level decision diagrams R Ubar, J Raik, A Jutman, M Jenihhin Design and Test Technology for Dependable Systems-on-chip, 92-118, 2011 | 15 | 2011 |
| Calculation of LFSR seed and polynomial pair for BIST applications A Jutman, A Tsertov, R Ubar 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and …, 2008 | 15 | 2008 |
| Parallel fault backtracing for calculation of fault coverage R Ubar, S Devadze, J Raik, A Jutman 13th Asia and South Pacific Design Automation Conference ASP-DAC, 667-672, 2008 | 15 | 2008 |
| Internet-based software for teaching test of digital circuits R Ubar, E Orasson, HD Wuttke 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No …, 2002 | 15 | 2002 |
Raimund UbarProfessor of Computer Engineering, Tallinn University of TechnologyVerified email at pld.ttu.ee
