| A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information T Oh, H Venkatram, U Moon IEEE Journal of Solid-State Circuits 49 (4), 961-971, 2014 | 69 | 2014 |
| A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR SM Yoo, TH Oh, JW Moon, SH Lee, UK Moon Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No …, 2002 | 62 | 2002 |
| A 71dB dynamic range third-order ΔΣ TDC using charge-pump M Gande, N Maghari, T Oh, UK Moon 2012 Symposium on VLSI Circuits (VLSIC), 168-169, 2012 | 52 | 2012 |
| A 15mW 0.2 mm/sup 2/50MS/s ADC with wide input range HC Choi, JH Kim, SM Yoo, KJ Lee, TH Oh, MJ Seo, JW Kim 2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006 | 38 | 2006 |
| Enhanced SAR ADC energy efficiency from the early reset merged capacitor switching algorithm J Guerber, H Venkatram, T Oh, UK Moon 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2361-2364, 2012 | 31 | 2012 |
| A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step Integrating Quantizer T Oh, N Maghari, U Moon IEEE Journal of Solid-State Circuits 48 (6), 1465-1474, 2013 | 27 | 2013 |
| A 5MHz BW 70.7 dB SNDR noise-shaped two-step quantizer based ΔΣ ADC T Oh, N Maghari, UK Moon 2012 Symposium on VLSI Circuits (VLSIC), 162-163, 2012 | 20 | 2012 |
| A 70MS/s 69.3 dB SNDR 38.2 fJ/conversion-step time-based pipelined ADC T Oh, H Venkatram, UK Moon 2013 Symposium on VLSI Circuits, C96-C97, 2013 | 17 | 2013 |
| Single-chip CMOS CCD camera interface based on digitally controlled capacitor-segment combination TH Oh, SH Lee IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2000 | 15 | 2000 |
| A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier H Venkatram, T Oh, K Sobue, K Hamashita, UK Moon 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 13 | 2014 |
| A 1.8 V 8-bit 250Msample/s Nyquist-rate CMOS pipelined ADC TH Oh, HY Lee, HJ Park, JW Kim 2004 IEEE International Symposium on Circuits and Systems (ISCAS) 1, I-I, 2004 | 12 | 2004 |
| A 3.0 V 12b 120 Msample/s CMOS pipelined ADC SM Yoo, TH Oh, HY Lee, KH Moon, JW Kim 2006 IEEE International Symposium on Circuits and Systems (ISCAS), 4 pp.-1026, 2006 | 11 | 2006 |
| A 14-b 30MS/s 0.75mm2 Pipelined ADC with On-Chip Digital Self-Calibration HY Lee, TH Oh, HJ Park, HS Lee, M Spaeth, JW Kim 2007 IEEE Custom Integrated Circuits Conference, 313-316, 2007 | 9 | 2007 |
| A 3.0 V 72mW 10b 100 MSample/s Nyquist-rate CMOS pipelined ADC in 0.54 mm/sup 2 TH Oh, SM Yoo, KH Moon, JW Kim 2006 IEEE International Symposium on Circuits and Systems (ISCAS), 4 pp., 2006 | 6* | 2006 |
| Parallel gain enhancement technique for switched-capacitor circuits H Venkatram, B Hershberg, T Oh, M Gande, K Sobue, K Hamashita, ... Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013 | 5 | 2013 |
| Analysis of residue integration sampling with improved jitter immunity T Oh, N Maghari, D Gubbins, UK Moon IEEE Transactions on Circuits and Systems II: Express Briefs 58 (7), 417-421, 2011 | 5 | 2011 |
| A 16b 10MS/s digitally self-calibrated ADC with time constant control TH Oh, HY Lee, JH Kim, HJ Park, KH Moon, JW Kim, HS Lee 2008 IEEE Custom Integrated Circuits Conference, 113-116, 2008 | 5 | 2008 |
| Class A+ amplifier with controlled positive feedback for discrete-time signal processing circuits H Venkatram, T Oh, J Guerber, UK Moon 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 428-431, 2012 | 4 | 2012 |
| Correlated jitter sampling for jitter cancellation in pipelined TDC T Oh, H Venkatram, J Guerber, UK Moon 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 810-813, 2012 | 3 | 2012 |
| Low voltage operational amplifier OH Tae-Hwan US Patent 7,449,951, 2008 | 2 | 2008 |
Sangmin YooSamsungVerified email at samsung.com
