Dae-Hyun Kim
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AVATAR: A variable-retention-time (VRT) aware refresh for DRAM systems
MK Qureshi, DH Kim, S Khan, PJ Nair, O Mutlu
2015 45th Annual IEEE/IFIP International Conference on Dependable Systems …, 2015
ArchShield: Architectural framework for assisting DRAM scaling by tolerating high error rates
PJ Nair, DH Kim, MK Qureshi
ACM SIGARCH Computer Architecture News 41 (3), 72-83, 2013
Architectural support for mitigating row hammering in dram memories
DH Kim, P Nair, M Qureshi
Computer Architecture Letters 14 (1), 9-12, 2015
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 graphics DRAM with low power and low noise data bus inversion
SJ Bae, KI Park, JD Ihm, HY Song, WJ Lee, HJ Kim, KH Kim, YS Park, ...
IEEE journal of solid-state circuits 43 (1), 121-131, 2008
A 60nm 6Gb/s/pin GDDR5 graphics DRAM with multifaceted clocking and ISI/SSN-reduction techniques
SJ Bae, YS Sohn, KI Park, KH Kim, DH Chung, JG Kim, SH Kim, MS Park, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW
SJ Bae, YS Sohn, TY Oh, SH Kim, YS Yang, DH Kim, SH Kwak, HS Seol, ...
2011 IEEE international solid-state circuits conference, 498-500, 2011
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM with 2.5 ns bank to bank active time and no bank group restriction
TY Oh, YS Sohn, SJ Bae, MS Park, JH Lim, YK Cho, DH Kim, DM Kim, ...
IEEE journal of solid-state circuits 46 (1), 107-118, 2010
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 graphics DRAM with low-power and low-noise data-bus inversion
JD Ihm, SJ Bae, KI Park, HY Song, WJ Lee, HJ Kim, KH Kim, HK Lee, ...
2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007
Photo-assisted electrochemical etching of a nano-gap trench with high aspect ratio for MEMS applications
HC Kim, DH Kim, K Chun
Journal of Micromechanics and Microengineering 16 (5), 906, 2006
A 7Gb/s/pin GDDR5 SDRAM with 2.5 ns bank-to-bank active time and no bank-group restriction
TY Oh, YS Sohn, SJ Bae, MS Park, JH Lim, YK Cho, DH Kim, DM Kim, ...
2010 IEEE International Solid-State Circuits Conference-(ISSCC), 434-435, 2010
A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface
SJ Bae, YS Sohn, T Oh, SH Kwak, DM Kim, DH Kim, YS Kim, YS Yang, ...
2010 Symposium on VLSI Circuits, 193-194, 2010
Method of training memory core and memory system
WJ Lee, DH Kim, SJ Bae, YS Sohn, TY Oh
US Patent App. 13/941,359, 2014
Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array
W Kim, CC Chen, DH Kim, L Milor
Transactions on Very Large Scale Integration (VLSI) Systems 24 (7), 2521-2534, 2016
Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits
K Yang, T Liu, R Zhang, DH Kim, L Milor
Microelectronics Reliability 76, 81-86, 2017
Optimization of Experimental Designs for System-Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown
DH Kim, SH Hsu, L Milor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019
Memory Reliability Estimation Degraded by TDDB Using Circuit-Level Accelerated Life Test
DH Kim, L Milor
International Reliability Physics Symposium (IRPS), 2017
Memory Yield and Lifetime Estimation Considering Aging Errors
DH Kim, LS Milor
International Integrated Reliability Workshop (IIRW), 2015
Devices, systems and methods with improved refresh address generation
WJ Lee, DH Kim, S Kim, JS Kim, YS Sohn
US Patent 9,355,703, 2016
ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs
DH Kim, L Milor
VLSI Test Symposium (VTS), 2016 IEEE 34th, 1-6, 2016
The Die-to-Die Calibrated Combined Model of Negative Bias Temperature Instability and Gate Oxide Breakdown from Device to System
S Cha, DH Kim, LS Milor
Microelectronics Reliability, 2015
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