| Genesys-pro: Innovations in test program generation for functional processor verification A Adir, E Almog, L Fournier, E Marcus, M Rimon, M Vinov, A Ziv IEEE Design & Test of Computers 21 (2), 84-93, 2004 | 291 | 2004 |
| A unified methodology for pre-silicon verification and post-silicon validation A Adir, S Copty, S Landa, A Nahir, G Shurek, A Ziv, C Meissner, ... 2011 Design, Automation & Test in Europe, 1-6, 2011 | 92 | 2011 |
| Modeling language and method for address translation design mechanisms in test generation A Koyfman, A Adir, R Emek, Y Katz, M Vinov US Patent 7,370,296, 2008 | 55 | 2008 |
| Information-flow models for shared memory with an application to the PowerPC architecture A Adir, H Attiya, G Shurek IEEE transactions on parallel and distributed systems 14 (5), 502-515, 2003 | 54 | 2003 |
| Threadmill: A post-silicon exerciser for multi-threaded processors A Adir, M Golubev, S Landa, A Nahir, G Shurek, V Sokhin, A Ziv Proceedings of the 48th Design Automation Conference, 860-865, 2011 | 53 | 2011 |
| Reaching coverage closure in post-silicon validation A Adir, A Nahir, A Ziv, C Meissner, J Schumann Haifa Verification Conference, 60-75, 2010 | 52 | 2010 |
| Highly specialized scenarios in random test generation R Emek, I Jaeger, T Schechner US Patent 8,161,440, 2012 | 44* | 2012 |
| Helayers: A tile tensors framework for large neural networks on encrypted data E Aharoni, A Adir, M Baruch, N Drucker, G Ezov, A Farkash, L Greenberg, ... arXiv preprint arXiv:2011.01805, 2020 | 41 | 2020 |
| Generating concurrent test-programs with collisions for multi-processor verification A Adir, G Shurek Seventh IEEE International High-Level Design Validation and Test Workshop …, 2002 | 40 | 2002 |
| Non-unique results in design verification by test programs A Adir US Patent 8,055,492, 2011 | 38 | 2011 |
| Automatic test program generation using extended conditional constraint satisfaction A Adir, E Bin, R Emek, K Shoikhet US Patent 7,386,521, 2008 | 32 | 2008 |
| Method and system for email phishing attempts identification and notification through organizational cognitive solutions A Adir, O Soceanu, L Greenberg US Patent 10,834,111, 2020 | 30 | 2020 |
| Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor A Adir, A Nahir, G Shurek, A Ziv, C Meissner, J Schumann Proceedings of the 48th Design Automation Conference, 569-574, 2011 | 30 | 2011 |
| Piparazzi: a test program generator for micro-architecture flow verification A Adir, E Bin, O Peled, A Ziv Eighth IEEE International High-Level Design Validation and Test Workshop, 23-28, 2003 | 30 | 2003 |
| Model-based hardware exerciser, device, system and method thereof A Adir, GE Shurek US Patent 7,945,888, 2011 | 29 | 2011 |
| Verification of transactional memory in power8 A Adir, D Goodman, D Hershcovich, O Hershkovitz, B Hickerson, K Holtz, ... Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 27 | 2014 |
| Systematic compliance checking of a process A Adir, S Asaf, L Fournier, I Jaeger, O Peled US Patent 7,673,261, 2010 | 24 | 2010 |
| Advances in simultaneous multithreading testcase generation methods JM Ludden, M Rimon, BG Hickerson, A Adir Hardware and Software: Verification and Testing: 6th International Haifa …, 2011 | 23 | 2011 |
| Adaptive test program generation A Adir, R Emek, E Marcus US Patent 6,925,405, 2005 | 21 | 2005 |
| DeepTrans-a model-based approach to functional verification of address translation mechanisms A Adir, R Emek, Y Katz, A Koyfman Proceedings. 4th International Workshop on Microprocessor Test and …, 2003 | 20 | 2003 |
Avi ZivResearch Staff Member, IBMVerified email at il.ibm.com
