Sorting, searching, and simulation in the mapreduce framework. MT Goodrich, N Sitchinava, Q Zhang ISAAC 7074, 374-383, 2011 | 236 | 2011 |

Fundamental parallel algorithms for private-cache chip multiprocessors L Arge, MT Goodrich, M Nelson, N Sitchinava Proceedings of the twentieth annual symposium on Parallelism in algorithms …, 2008 | 153 | 2008 |

A reconfigurable shared scan-in architecture S Samaranayake, E Gizdarski, N Sitchinava, F Neuveux, R Kapur, ... Proceedings. 21st VLSI Test Symposium, 2003., 9-14, 2003 | 114 | 2003 |

Changing the scan enable during shift N Sitchinava, E Gizdarski, S Samaranayake, F Neuveux, R Kapur, ... 22nd IEEE VLSI Test Symposium, 2004. Proceedings., 73-78, 2004 | 89 | 2004 |

Parallel external memory graph algorithms L Arge, MT Goodrich, N Sitchinava 2010 IEEE International Symposium on Parallel & Distributed Processing …, 2010 | 45 | 2010 |

Guard placement for efficient point-in-polygon proofs D Eppstein, MT Goodrich, N Sitchinava Proceedings of the twenty-third annual symposium on Computational geometry …, 2007 | 39* | 2007 |

Dynamic scan: Driving down the cost of test S Samaranayake, N Sitchinava, R Kapur, MB Amin, TW Williams Computer 35 (10), 63-68, 2002 | 36 | 2002 |

Efficient parallel and external matching M Birn, V Osipov, P Sanders, C Schulz, N Sitchinava Euro-Par 2013 Parallel Processing: 19th International Conference, Aachen …, 2013 | 30 | 2013 |

Lower bounds in the asymmetric external memory model R Jacob, N Sitchinava Proceedings of the 29th ACM Symposium on Parallelism in Algorithms and …, 2017 | 27 | 2017 |

Dynamically reconfigurable shared scan-in test architecture R Kapur, N Sitchinava, S Samaranayake, E Gizdarski, F Neuveux, ... US Patent 7,418,640, 2008 | 26 | 2008 |

Parallel algorithms in geometry MT Goodrich, N Sitchinava Handbook of Discrete and Computational Geometry, 1225-1239, 2017 | 20 | 2017 |

Geometric algorithms for private-cache chip multiprocessors D Ajwani, N Sitchinava, N Zeh Algorithms–ESA 2010: 18th Annual European Symposium, Liverpool, UK …, 2010 | 20 | 2010 |

A parallel buffer tree N Sitchinava, N Zeh Proceedings of the twenty-fourth annual ACM symposium on Parallelism in …, 2012 | 19 | 2012 |

Dynamically reconfigurable shared scan-in test architecture R Kapur, N Sitchinava, S Samaranayake, E Gizdarski, FJ Neuveux, ... US Patent 7,900,105, 2011 | 17 | 2011 |

Provably efficient GPU algorithms N Sitchinava, V Weichert CoRR, abs/1306.5076, 2013 | 16 | 2013 |

Analysis-driven engineering of comparison-based sorting algorithms on GPUs B Karsin, V Weichert, H Casanova, J Iacono, N Sitchinava Proceedings of the 2018 International Conference on Supercomputing, 86-95, 2018 | 14 | 2018 |

On the complexity of list ranking in the parallel external memory model R Jacob, T Lieber, N Sitchinava Mathematical Foundations of Computer Science 2014: 39th International …, 2014 | 14 | 2014 |

Dynamically reconfigurable shared scan-in test architecture R Kapur, N Sitchinava, S Samaranayake, E Gizdarski, FJ Neuveux, ... US Patent 7,596,733, 2009 | 13 | 2009 |

On (dynamic) range minimum queries in external memory L Arge, J Fischer, P Sanders, N Sitchinava Algorithms and Data Structures: 13th International Symposium, WADS 2013 …, 2013 | 11 | 2013 |

Beyond binary search: parallel in-place construction of implicit search tree layouts K Berney, H Casanova, B Karsin, N Sitchinava IEEE Transactions on Computers 71 (5), 1104-1116, 2021 | 10 | 2021 |