Jong-Ho Lee
Jong-Ho Lee
Department of Electrical and Computer Engineering, Seoul National University
Verified email at - Homepage
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Bias-stress-induced stretched-exponential time dependence of threshold voltage shift in InGaZnO thin film transistors
JM Lee, HIK In-Tak Cho, Jong-Ho Lee
Apppl. Phys. Lett 93, 093504, 2008
Three-dimensional NAND flash architecture design based on single-crystalline stacked array
Y Kim, JG Yun, SH Park, W Kim, JY Seo, M Kang, KC Ryoo, JH Oh, ...
IEEE Transactions on Electron Devices 59 (1), 35-45, 2011
Double-gate FinFET device and fabricating method thereof
J Lee
US Patent 6,885,055, 2005
Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers
T Park, S Choi, DH Lee, JR Yoo, BC Lee, JY Kim, CG Lee, KK Chi, ...
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 2003
Single-crystalline Si stacked array (STAR) NAND flash memory
JG Yun, G Kim, JE Lee, Y Kim, WB Shim, JH Lee, H Shin, JD Lee, ...
IEEE Transactions on Electron Devices 58 (4), 1006-1014, 2011
Method for making a silicon-on-insulator MOS transistor using a selective SiGe epitaxy
JH Lee, JS Lyu, BW Kim
US Patent 6,048,756, 2000
Charge trapping and detrapping characteristics in amorphous InGaZnO TFTs under static and dynamic stresses
IT Cho, JM Lee, JH Lee, HI Kwon
Semiconductor Science and Technology 24 (1), 015013, 2008
Flash memory element and manufacturing method thereof
JH Lee, HC Shin
US Patent 6,768,158, 2004
Water-soluble thin film transistors and circuits based on amorphous indium–gallium–zinc oxide
JAR Sung Hun Jin, Seung-Kyun Kang, In-Tak Cho, Sang Youn Han, Ha Uk Chung ...
ACS applied materials & interfaces 7 (15), 8268-8274, 2015
Comparative study of electrical instabilities in top-gate InGaZnO thin film transistors with and gate dielectrics
JM Lee, IT Cho, JH Lee, WS Cheong, CS Hwang, HI Kwon
Applied Physics Letters 94 (22), 222112, 2009
Room temperature single electron effects in a Si nano-crystal memory
I Kim, S Han, K Han, J Lee, H Shin
IEEE Electron Device Letters 20 (12), 630-631, 1999
Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy
JH Lee, G Taraschi, A Wei, TA Langdo, EA Fitzgerald, DA Antoniadis
International Electron Devices Meeting 1999. Technical Digest (Cat. No …, 1999
Vertical channel field effect transistors having insulating layers thereon
T Park, EJ Yoon, UI Chung, SY Choi, J Lee
US Patent 7,148,541, 2006
Silicon-based floating-body synaptic transistor with frequency-dependent short-and long-term memories
H Kim, J Park, MW Kwon, JH Lee, BG Park
IEEE Electron Device Letters 37 (3), 249-252, 2016
Scaling effect on silicon nitride memristor with highly doped Si substrate
S Kim, S Jung, MH Kim, YC Chen, YF Chang, KC Ryoo, S Cho, JH Lee, ...
Small 14 (19), 1704062, 2018
Low-frequency noise in amorphous indium–gallium–zinc-oxide thin-film transistors
JM Lee, WS Cheong, CS Hwang, IT Cho, HI Kwon, JH Lee
IEEE electron device letters 30 (5), 505-507, 2009
Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (bulk FinFETs)
TS Park, HJ Cho, JD Choe, SY Han, D Park, K Kim, E Yoon, JH Lee
IEEE Transactions on Electron Devices 53 (3), 481-487, 2006
Adaptive Learning Rule for Hardware-based Deep Neural Networks Using Electronic Synapse Devices
S Lim, JH Bae, JH Eum, S Lee, CH Kim, BG Park, JH Lee
Neural Computing and Applications, 1-16, 2018
Accurate analysis of conduction and resistive-switching mechanisms in double-layered resistive-switching memory devices
JK Lee, S Jung, J Park, SW Chung, J Sung Roh, SJ Hong, I Hwan Cho, ...
Applied Physics Letters 101 (10), 103506, 2012
PMOS body-tied FinFET (Omega MOSFET) characteristics
T Park, D Park, JH Chung, EJ Yoon, SM Kim, HJ Cho, JD Choe, JH Choi, ...
61st Device Research Conference. Conference Digest (Cat. No. 03TH8663), 33-34, 2003
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