| LDO linear regulator with improved transient response M Shrivas, M Jain US Patent 8,344,713, 2013 | 47 | 2013 |
| A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, ringamp-based pipelined-SAR ADC With background calibration and dynamic reference regulation in 16-nm CMOS J Lagos, N Markulić, B Hershberg, D Dermit, M Shrivas, E Martens, ... IEEE Journal of Solid-State Circuits 57 (4), 1112-1124, 2022 | 32 | 2022 |
| A 10.56 Gbit/s,-27.8 dB EVM polar transmitter at 60 GHz in 28nm CMOS J Nguyen, K Khalaf, S Brebels, M Shrivas, K Vaesen, P Wambacq 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 179-182, 2020 | 9 | 2020 |
| A 1.67-GSps TI 10-bit ping-pong SAR ADC with 51-dB SNDR in 16-nm FinFET D Dermit, M Shrivas, K Bunsen, JL Benites, J Craninckx, E Martens IEEE Solid-State Circuits Letters 3, 150-153, 2020 | 9 | 2020 |
| A Compact 8-bit, 8 GS/s 8× TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW E Martens, D Dermit, M Shrivas, S Nagata, J Craninckx 2021 Symposium on VLSI Circuits, 1-2, 2021 | 8 | 2021 |
| Standby control circuit and method S Ramakrishnan, K Abhishek, A Goel, A Gupta, C Gupta, M Shrivas, ... US Patent 7,952,401, 2011 | 3 | 2011 |
| Design of a 10.56-Gb/s 64-QAM Polar Transmitter at 60 GHz in 28-nm CMOS J Nguyen, K Khalaf, X Tang, S Brebels, K Vaesen, M Shrivas, P Wambacq IEEE Journal of Solid-State Circuits, 2023 | | 2023 |
| A 10.1 ENOB, 6.2 fJ/con.-step, 500MS/s ringamp-based pipelined-SAR ADC with background calibration and dynamic reference regulation in 16nm CMOS J Lagos Benites, N Markulic, B Hershberg, D Dermit, M Shrivas, ... | | 2021 |
| 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) JHD Nguyen, K Khalaf, S Brebels, M Shrivas, K Vaesen, P Wambacq 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 179-182, 2020 | | 2020 |
Jan CraninckxFellow, IMECVerified email at imec.be
