| NEMEA: a framework for network traffic analysis T Cejka, V Bartos, M Svepes, Z Rosa, H Kubatova 2016 12th International Conference on Network and Service Management (CNSM …, 2016 | 84 | 2016 |
| P4-to-vhdl: Automatic generation of 100 gbps packet parsers P Benácek, V Pu, H Kubátová 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom …, 2016 | 65 | 2016 |
| FPGA based design of the railway's interlocking equipments R Dobias, H Kubatova Euromicro Symposium on Digital System Design, 2004. DSD 2004., 467-473, 2004 | 59 | 2004 |
| Fault tolerant system design method based on self-checking circuits P Kubalík, P Fiser, H Kubátová 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2 pp., 2006 | 39 | 2006 |
| Parity driven reconfigurable duplex system J Borecký, M Kohlík, H Kubátová Microprocessors and Microsystems 52, 251-260, 2017 | 38 | 2017 |
| P4-To-VHDL: Automatic generation of high-speed input and output network blocks P Benáček, V Puš, H Kubátová, T Čejka Microprocessors and Microsystems 56, 22-33, 2018 | 33 | 2018 |
| Fault classification for self-checking circuits implemented in FPGA L Kafka, P Kubalík, H Kubátová, O Novák Proceedings of IEEE Design and Diagnostics of Electronic Circuits and …, 2005 | 30 | 2005 |
| Dependable design technique for system-on-chip P Kubalík, H Kubátová Journal of Systems Architecture 54 (3-4), 452-464, 2008 | 29 | 2008 |
| Dependable design for fpga based on duplex system and reconfiguration P Kubalik, R Dobias, H Kubatova 9th EUROMICRO Conference on Digital System Design (DSD'06), 139-145, 2006 | 29 | 2006 |
| FC-Min: A fast multi-output Boolean minimizer P Fiser, J Hlavicka, H Kubatova Euromicro Symposium on Digital System Design, 2003. Proceedings., 451-454, 2003 | 29 | 2003 |
| Flexible two-level Boolean minimizer BOOM-II and its applications P Fiser, H Kubátová 9th EUROMICRO Conference on Digital System Design (DSD'06), 369-376, 2006 | 27 | 2006 |
| Parity codes used for on-line testing in FPGA P Kubalík, H Kubátová Acta Polytechnica 45 (6), 2005 | 26 | 2005 |
| Two-level boolean minimizer boom-ii P Fišer, H Kubátová Proc. 6th Int. Workshop on Boolean Problems (IWSBP'04), Freiberg, Germany 23 …, 2004 | 23 | 2004 |
| Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches P Socha, V Miškovský, H Kubátová, M Novotný 2017 IEEE 20th International Symposium on Design and Diagnostics of …, 2017 | 22 | 2017 |
| Reliable railway station system based on regular structure implemented in FPGA J Borecky, P Kubalik, H Kubatova 2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009 | 22 | 2009 |
| Stream-wise detection of surreptitious traffic over DNS T Cejka, Z Rosa, H Kubatova 2014 IEEE 19th International Workshop on Computer Aided Modeling and Design …, 2014 | 21 | 2014 |
| Finite state machine implementation in FPGAs MA Adamski, A Karatkevich, M Wegrzyn, H Kubátová Design of Embedded Control Systems, 175-184, 2005 | 21 | 2005 |
| Fault models usability study for on-line tested FPGA J Borecky, M Kohlik, P Kubalik, H Kub 2011 14th Euromicro Conference on Digital System Design, 287-290, 2011 | 18 | 2011 |
| An efficient multiple-parity generator design for on-line testing on FPGA P Fišer, P Kubalík, H Kubátová 2008 11th EUROMICRO Conference on Digital System Design Architectures …, 2008 | 17 | 2008 |
| An efficient mixed-mode BIST technique P Fišer, H Kubátová Vectors 1 (1010X), 11011, 2004 | 17 | 2004 |
