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Yuetsu Kodama
Yuetsu Kodama
Senior Scientist, Center for Computational Science, RIKEN
Verified email at riken.go.jp
Title
Cited by
Cited by
Year
An architecture of a dataflow single chip processor
S Sakai, Y Yamaguchi, K Hiraki, Y Kodama, T Yuba
ACM SIGARCH Computer Architecture News 17 (3), 46-53, 1989
3211989
The gem5 simulator: Version 20.0+
J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ...
arXiv preprint arXiv:2007.03152, 2020
3022020
Co-design for a64fx manycore processor and” fugaku”
M Sato, Y Ishikawa, H Tomita, Y Kodama, T Odajima, M Tsuji, H Yashiro, ...
SC20: International Conference for High Performance Computing, Networking …, 2020
1772020
Thread-based programming for the EM-4 hybrid dataflow machine
M Sato, Y Kodama, S Sakai, Y Yamaguchi, Y Koumura
ACM SIGARCH Computer Architecture News 20 (2), 146-155, 1992
1131992
The EM-X parallel computer: Architecture and basic performance
Y Kodama, H Sakane, M Sato, H Yamana, S Sakai, Y Yamaguchi
ACM SIGARCH Computer Architecture News 23 (2), 14-23, 1995
851995
GNET-1: Gigabit Ethernet network testbed
Y Kodama, T Kudoh, R Takano, H Sato, O Tatebe, S Sekiguchi
2004 IEEE International Conference on Cluster Computing (IEEE Cat. No …, 2004
832004
Load balanced parallel radix sort
A Sohn, Y Kodama
Proceedings of the 12th international conference on Supercomputing, 305-312, 1998
831998
Efficient mpi collective operations for clusters in long-and-fast networks
M Matsuda, T Kudoh, Y Kodama, R Takano, Y Ishikawa
2006 IEEE International Conference on Cluster Computing, 1-9, 2006
702006
XcalableACC: Extension of XcalableMP PGAS language using OpenACC for accelerator clusters
M Nakao, H Murai, T Shimosaka, A Tabuchi, T Hanawa, Y Kodama, ...
2014 First Workshop on Accelerator Programming using Directives, 27-36, 2014
632014
Design and evaluation of precise software pacing mechanisms for fast long-distance networks
R Takano, T Kudoh, Y Kodama, M Matsuda, H Tezuka, Y Ishikawa
PFLDnet 2005, 2005
632005
Interconnection network for tightly coupled accelerators architecture
T Hanawa, Y Kodama, T Boku, M Sato
2013 IEEE 21st Annual Symposium on High-Performance Interconnects, 79-82, 2013
592013
A prototype of a highly parallel dataflow machine EM-4 and its preliminary evaluation
Y Kodama, S Sakai, Y Yamaguchi
Future Generation Computer Systems 7 (2-3), 199-209, 1992
571992
Super-threading: Architectural and software mechanisms for optimizing parallel computation
S Sakai, K Okamoto, H Matsuoka, H Hirono, Y Kodama, M Sato
Proceedings of the 7th international conference on Supercomputing, 251-260, 1993
541993
Preliminary performance evaluation of the Fujitsu A64FX using HPC applications
T Odajima, Y Kodama, M Tsuji, M Matsuda, Y Maruyama, M Sato
2020 IEEE international conference on cluster computing (cluster), 523-530, 2020
502020
Information delivery system, delivery request program, transfer program, delivery program, and the like
H Matsuo, Y Hibino, Y Kiyohara, H Suzuki, K Ushiyama, K Iijima, T Kudo, ...
US Patent 7,839,867, 2010
472010
Tightly coupled accelerators architecture for minimizing communication latency among accelerators
T Hanawa, Y Kodama, T Boku, M Sato
2013 IEEE International Symposium on Parallel & Distributed Processing …, 2013
422013
Information delivery system, delivery request program, transfer program, delivery program, and the like
Y Kiyohara, Y Hibino, H Suzuki, K Ushiyama, H Matsuo, K Iijima, T Kudo, ...
US Patent 8,195,764, 2012
402012
Evaluation of power management control on the supercomputer fugaku
Y Kodama, T Odajima, E Arima, M Sato
2020 IEEE International Conference on Cluster Computing (CLUSTER), 484-493, 2020
372020
PEACH2: an FPGA-based PCIe network device for tightly coupled accelerators
Y Kodama, T Hanawa, T Boku, M Sato
ACM SIGARCH Computer Architecture News 42 (4), 3-8, 2014
362014
EMC-Y: Parallel processing element optimizing communication and computation
Y Kodama, Y Koumura, M Sato, H Sakane, S Sakai, Y Yamaguchi
Proceedings of the 7th international conference on Supercomputing, 167-174, 1993
331993
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