High-frequency scalable electrical model and analysis of a through silicon via (TSV) J Kim, JS Pak, J Cho, E Song, J Cho, H Kim, T Song, J Lee, H Lee, K Park, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (2 …, 2011 | 496 | 2011 |
Stack package having guard ring which insulates through-via interconnection plug and method for manufacturing the same SM Kim, MS Suh US Patent 7,525,186, 2009 | 234 | 2009 |
Modeling and analysis of through-silicon via (TSV) noise coupling and suppression using a guard ring J Cho, E Song, K Yoon, JS Pak, J Kim, W Lee, T Song, K Kim, J Lee, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (2 …, 2011 | 188 | 2011 |
Measurement of stresses in Cu and Si around through-silicon via by synchrotron X-ray microdiffraction for 3-dimensional integrated circuits AS Budiman, HAS Shin, BJ Kim, SH Hwang, HY Son, MS Suh, QH Chung, ... Microelectronics Reliability 52 (3), 530-533, 2012 | 147 | 2012 |
Stack package utilizing through vias and re-distribution lines SH Lee, MS Suh US Patent 7,598,617, 2009 | 140 | 2009 |
Effects of plating parameters on alloy composition and microstructure of Sn–Bi electrodeposits from methane sulphonate bath MS Suh, CJ Park, HS Kwon Surface and Coatings Technology 200 (11), 3527-3532, 2006 | 87 | 2006 |
Method for manufacturing semiconductor package KW Han, CJ Park, MS Suh, SC Kim, SM Kim, ST Yang, SH Lee, JH Kim, ... US Patent 7,795,139, 2010 | 85 | 2010 |
Growth kinetics of Cu–Sn intermetallic compounds at the interface of a Cu substrate and 42Sn–58Bi electrodeposits, and the influence of the intermetallic compounds on the shear … MS Suh, CJ Park, HS Kwon Materials Chemistry and Physics 110 (1), 95-99, 2008 | 35 | 2008 |
Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same MS Suh US Patent 7,973,414, 2011 | 31 | 2011 |
Effects of plating conditions on the microstructure of 80Sn 20Pb electrodeposits from an organic sulphonate bath JH Kim, MS Suh, HS Kwon Surface and Coatings Technology 78 (1-3), 56-63, 1996 | 31 | 1996 |
Semiconductor package module JH Kim, MS Suh, SC Kim, ST Yang, SH Lee US Patent 8,395,245, 2013 | 25 | 2013 |
Cube semiconductor package composed of a plurality of stacked together and interconnected semiconductor chip modules MS Suh, SH Lee US Patent 8,299,592, 2012 | 24 | 2012 |
Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same MS Suh US Patent 8,232,654, 2012 | 24 | 2012 |
Method of manufacturing wafer level stack package MS Suh, SM Kim US Patent 7,507,637, 2009 | 22 | 2009 |
Semiconductor package for improving characteristics for transmitting signals and power JH Kim, MS Suh, ST Yang US Patent 7,859,115, 2010 | 21 | 2010 |
Joule heating effect on the electromigration lifetimes and failure mechanisms of Sn-3.5 Ag solder bump JH Lee, YD Lee, YB Park, ST Yang, MS Suh, QH Chung, KY Byun 2007 Proceedings 57th Electronic Components and Technology Conference, 1436-1441, 2007 | 20 | 2007 |
Study of stresses and plasticity in through-silicon via structures for 3D interconnects by X-ray micro-beam diffraction T Jiang, C Wu, N Tamura, M Kunz, BG Kim, HY Son, MS Suh, J Im, ... IEEE Transactions on Device and Materials Reliability 14 (2), 698-703, 2014 | 19 | 2014 |
Semiconductor package having an internal cooling system MS Suh, CJ Park US Patent 8,159,065, 2012 | 16 | 2012 |
Electromigration and thermomigration characteristics in flip chip Sn-3.5 Ag solder bump JH Lee, GT Lim, ST Yang, MS Suh, QH Chung, KY Byun, YB Park JOURNAL OF THE KOREAN INSTITUTE OF METALS AND MATERIALS 46 (5), 310-314, 2008 | 14 | 2008 |
Stack package and method for manufacturing the same SM Kim, MS Suh US Patent 7,871,925, 2011 | 12 | 2011 |