| A 10 b, 20 Msample/s, 35 mW pipeline A/D converter TB Cho, PR Gray IEEE journal of solid-state circuits 30 (3), 166-172, 1995 | 955 | 1995 |
| A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications JC Rudell, JJ Ou, TB Cho, G Chien, F Brianti, JA Weldon, PR Gray IEEE Journal of Solid-State Circuits 32 (12), 2071-2088, 1997 | 724 | 1997 |
| A 1.9 GHz wide-band IF double conversion CMOS integrated receiver for cordless telephone applications JC Rudell, JJ Ou, TB Cho, G Chien, F Brianti, JA Weldon, PR Gray 1997 IEEE International Solids-State Circuits Conference. Digest of …, 1997 | 157 | 1997 |
| A 10-bit, 20-MS/s, 35-mW pipeline A/D converter TB Cho, PR Gray Proceedings of IEEE Custom Integrated Circuits Conference-CICC'94, 499-502, 1994 | 130 | 1994 |
| A 28-nm 75-fsrms Analog Fractional- Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle … W Wu, CW Yao, K Godbole, R Ni, PY Chiang, Y Han, Y Zuo, A Verma, ... IEEE Journal of Solid-State Circuits 54 (5), 1254-1265, 2019 | 124 | 2019 |
| A 2.4-GHz dual-mode 0.18-/spl mu/m CMOS transceiver for Bluetooth and 802.11 b TB Cho, D Kang, CH Heng, BS Song IEEE journal of solid-state circuits 39 (11), 1916-1926, 2004 | 117 | 2004 |
| Low-power low-voltage analog-to-digital conversion techniques using pipelined architectures TB Cho University of California, Berkeley, 1995 | 112 | 1995 |
| A single-chip CMOS direct-conversion transceiver for 900 MHz spread-spectrum digital cordless phones T Cho, E Dukatz, M Mack, D Macnally, M Marringa, S Mehta, C Nilson, ... 1999 IEEE International Solid-State Circuits Conference. Digest of Technical …, 1999 | 101 | 1999 |
| Antenna interface DE MacNally, TB Cho US Patent 6,735,418, 2004 | 79 | 2004 |
| A sub-6-GHz 5G new radio RF transceiver supporting EN-DC with 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS J Lee, S Han, J Lee, B Kang, J Bae, J Jang, S Oh, JS Chang, S Kang, ... IEEE Journal of Solid-State Circuits 54 (12), 3541-3552, 2019 | 73 | 2019 |
| Reconfigurable analog baseband for a single-chip dual-mode transceiver T Cho US Patent 7,283,840, 2007 | 70 | 2007 |
| A 14-nm 0.14-psrmsFractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration CW Yao, R Ni, C Lau, W Wu, K Godbole, Y Zuo, S Ko, NS Kim, S Han, I Jo, ... IEEE Journal of Solid-State Circuits 52 (12), 3446-3457, 2017 | 63 | 2017 |
| A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO W Wu, CW Yao, C Guo, PY Chiang, L Chen, PK Lau, Z Bai, SW Son, ... IEEE Journal of Solid-State Circuits 56 (12), 3756-3767, 2021 | 48 | 2021 |
| A power-optimized CMOS baseband channel filter and ADC for cordless applications TB Cho, G Chien, F Brianti, PR Gray 1996 Symposium on VLSI Circuits. Digest of Technical Papers, 64-65, 1996 | 47 | 1996 |
| 15.1 An 88%-Efficiency Supply Modulator Achieving 1.08 μs/V Fast Transition and 100MHz Envelope-Tracking Bandwidth for 5G New Radio RF Power Amplifier JS Paek, D Kim, JS Bang, J Baek, J Choi, T Nomiyama, J Han, Y Choo, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 238-240, 2019 | 44 | 2019 |
| 32.2 A 14nm analog sampling fractional-N PLL with a digital-to-time converter range-reduction technique achieving 80fs integrated jitter and 93fs at near-integer channels W Wu, CW Yao, C Guo, PY Chiang, PK Lau, L Chen, SW Son, TB Cho 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 444-446, 2021 | 39 | 2021 |
| A− 137 dBm/Hz noise, 82% efficiency AC-coupled hybrid supply modulator with integrated buck-boost converter JS Paek, SC Lee, YS Youn, D Kim, JH Choi, J Jung, YH Choo, SJ Lee, ... IEEE Journal of Solid-State Circuits 51 (11), 2757-2768, 2016 | 39 | 2016 |
| NB-IoT and GNSS all-in-one system-on-chip integrating RF transceiver, 23-dBm CMOS power amplifier, power management unit, and clock management system for low cost solution J Lee, J Han, CL Lo, J Lee, W Kim, S Kim, B Kang, J Han, S Jung, ... IEEE Journal of Solid-State Circuits 55 (12), 3400-3413, 2020 | 38 | 2020 |
| 20.7 An RF-PA supply modulator achieving 83% efficiency and− 136dBm/Hz noise for LTE-40MHz and GSM 35dBm applications JS Paek, YS Youn, JH Choi, DS Kim, JH Jung, YH Choo, SJ Lee, SC Lee, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 354-355, 2016 | 38 | 2016 |
| A low spur fractional-N digital PLL for 802.11 a/b/g/n/ac with 0.19 psrms jitter CW Yao, L Lin, B Nissim, H Arora, T Cho 2011 Symposium on VLSI Circuits-Digest of Technical Papers, 110-111, 2011 | 38 | 2011 |
