| Near-data processing: Insights from a micro-46 workshop R Balasubramonian, J Chang, T Manning, JH Moreno, R Murphy, R Nair, ... IEEE Micro 34 (4), 36-42, 2014 | 309 | 2014 |
| Active memory cube: A processing-in-memory architecture for exascale systems R Nair, SF Antao, C Bertolli, P Bose, JR Brunheroto, T Chen, CY Cher, ... IBM Journal of Research and Development 59 (2/3), 17: 1-17: 14, 2015 | 226 | 2015 |
| Environment for PowerPC microarchitecture exploration M Moudgill, JD Wellman, JH Moreno IEEE Micro 19 (3), 15-25, 1999 | 153 | 1999 |
| Introduction to digital systems MD Ercegovac, JH Moreno, T Lang John Wiley & Sons, Inc., 1998 | 143 | 1998 |
| Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor MK Ebcioglu, DA Luick, JH Moreno, GM Silberman, PB Winterfield US Patent 5,625,835, 1997 | 96 | 1997 |
| Validation of Turandot, a fast processor model for microarchitecture exploration M Moudgill, P Bose, JH Moreno 1999 IEEE International Performance, Computing and Communications Conference …, 1999 | 83 | 1999 |
| Object-code compatible representation of very long instruction word programs JH Moreno US Patent 5,951,674, 1999 | 78 | 1999 |
| Method and apparatus for memory prefetching based on intra-page usage history JH Moreno, JA Rivers, JD Wellman US Patent 6,678,795, 2004 | 70 | 2004 |
| Introdução aos sistemas digitais MD Ercegovac, T Lang, JH Moreno Bookman, 2000 | 67 | 2000 |
| Apparatus region-based detection of interference among reordered memory operations in a processor JH Moreno, M Moudgill US Patent 5,918,005, 1999 | 65 | 1999 |
| Method and apparatus for reordering memory operations in a processor JH Moreno, M Moudgill US Patent 5,758,051, 1998 | 64 | 1998 |
| Matrix computations on systolic-type meshes: An introduction to the multimesh graph method JH Moreno, T Lang Computer 23 (4), 32-51, 1990 | 64 | 1990 |
| Method and apparatus for reducing logic activity in a microprocessor using reduced bit width slices that are enabled or disabled depending on operation width JA Rivers, JH Moreno, VR Cuppu US Patent 6,948,051, 2005 | 63 | 2005 |
| Trends in compilable DSP architecture J Glossner, J Moreno, M Moudgill, J Derby, E Hokenek, D Meltzer, ... 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and …, 2000 | 54 | 2000 |
| Object code compatible representation of very long instruction word programs JH Moreno US Patent 5,669,001, 1997 | 51 | 1997 |
| True value: assessing and optimizing the cost of computing at the data center level J Karidis, JE Moreira, J Moreno Proceedings of the 6th ACM conference on Computing frontiers, 185-192, 2009 | 43 | 2009 |
| An innovative low-power high-performance programmable signal processor for digital communications JH Moreno, V Zyuban, U Shvadron, FD Neeser, JH Derby, MS Ware, ... IBM Journal of Research and Development 47 (2.3), 299-326, 2003 | 42 | 2003 |
| Branch on cache hit/miss for compiler-assisted miss delay tolerance CM Barton III, PK Dubey, JH Moreno US Patent 5,761,515, 1998 | 42 | 1998 |
| Matrix Computations on Systolic-Type Arrays JH Moreno, T Lang Boston, MA: Springer US: Imprint: Springer,, 1992 | 42* | 1992 |
| Cache with selective least frequently used or most frequently used cache line replacement RE Matick, JH Moreno, MS Ware US Patent 7,133,971, 2006 | 36 | 2006 |
