NoC synthesis flow for customized domain specific multiprocessor systems-on-chip D Bertozzi, A Jalabert, S Murali, R Tamhankar, S Stergiou, L Benini, ... IEEE transactions on parallel and distributed systems 16 (2), 113-129, 2005 | 747 | 2005 |
Xpipes: A network-on-chip architecture for gigascale systems-on-chip D Bertozzi, L Benini IEEE circuits and systems magazine 4 (2), 18-31, 2004 | 651 | 2004 |
Networks on chips L Benini, G De Micheli, TT Ye Morgan Kaufmann, 2006 | 368 | 2006 |
Mparm: Exploring the multi-processor soc design space with systemc L Benini, D Bertozzi, A Bogliolo, F Menichelli, M Olivieri Journal of VLSI signal processing systems for signal, image and video …, 2005 | 353 | 2005 |
Error control schemes for on-chip communication links: the energy-reliability tradeoff D Bertozzi, L Benini, G De Micheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 293 | 2005 |
Xpipes: a latency insensitive parameterized network-on-chip architecture for multi-processor SoCs M Dall'Osso, G Biccari, L Giovannini, D Bertozzi, L Benini 2012 IEEE 30th International Conference on Computer Design (ICCD), 45-48, 2012 | 282 | 2012 |
Analyzing on-chip communication in a MPSoC environment M Loghi, F Angiolini, D Bertozzi, L Benini, R Zafalon Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 248 | 2004 |
Low power error resilient encoding for on-chip data buses D Bertozzi, L Benini, G De Micheli Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002 | 234 | 2002 |
Supporting task migration in multi-processor systems-on-chip: a feasibility study S Bertozzi, A Acquaviva, D Bertozzi, A Poggiali Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 220 | 2006 |
Network-on-chip architectures and design methods L Benini, D Bertozzi IEE Proceedings-Computers and Digital Techniques 152 (2), 261-272, 2005 | 202 | 2005 |
/spl times/pipes Lite: a synthesis oriented design library for networks on chips S Stergiou, F Angiolini, S Carta, L Raffo, D Bertozzi, G De Micheli Design, Automation and Test in Europe, 1188-1193, 2005 | 192 | 2005 |
SystemC cosimulation and emulation of multiprocessor SoC designs L Benini, D Bertozzi, D Bruni, N Drago, F Fummi, M Poncino Computer 36 (4), 53-59, 2003 | 187 | 2003 |
A high-efficiency wind-flow energy harvester using micro turbine D Carli, D Brunelli, D Bertozzi, L Benini SPEEDAM 2010, 778-783, 2010 | 147 | 2010 |
Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip M Ruggiero, A Guerri, D Bertozzi, F Poletti, M Milano Proceedings of the Design Automation & Test in Europe Conference 1, 6 pp., 2006 | 139 | 2006 |
Fault tolerance overhead in network-on-chip flow control schemes A Pullini, F Angiolini, D Bertozzi, L Benini Proceedings of the 18th annual symposium on Integrated circuits and system …, 2005 | 139 | 2005 |
Designing network on-chip architectures in the nanoscale era J Flich, D Bertozzi CRC press, 2010 | 119 | 2010 |
Addressing manufacturing challenges with cost-efficient fault tolerant routing S Rodrigo, J Flich, A Roca, S Medardoni, D Bertozzi, J Camacho, F Silla, ... 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, 25-32, 2010 | 118 | 2010 |
Performance analysis of arbitration policies for SoC communication architectures F Poletti, D Bertozzi, L Benini, A Bogliolo Design Automation for Embedded Systems 8, 189-210, 2003 | 110 | 2003 |
Allocation and scheduling for MPSoCs via decomposition and no-good generation L Benini, D Bertozzi, A Guerri, M Milano Principles and Practice of Constraint Programming-CP 2005: 11th …, 2005 | 83 | 2005 |
Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis L Ramini, P Grani, S Bartolini, D Bertozzi 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 82 | 2013 |