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Tawfiq Musah
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Year
Wireless communication technology, apparatuses, and methods
E Alpman, AL Amadjikpe, O Asaf, K Azadet, R Banin, M Baryakh, A Bazov, ...
US Patent 11,424,539, 2022
2152022
Wireline receiver circuitry having collaborative timing recovery
T Musah, G Keskin, G Balamurugan, JE Jaussi, BK Casper
US Patent 9,374,250, 2016
1142016
A 4–32 Gb/s bidirectional link with 3-tap FFE/6-tap DFE and collaborative CDR in 22 nm CMOS
T Musah, JE Jaussi, G Balamurugan, S Hyvonen, TC Hsueh, G Keskin, ...
IEEE Journal of Solid-State Circuits 49 (12), 3079-3090, 2014
642014
Low power high speed receiver with reduced decision feedback equalizer samplers
T Musah, H Venkatram, BK Casper
US Patent 10,341,145, 2019
542019
Design of a 79 dB 80 MHz 8X-OSR hybrid delta-sigma/pipelined ADC
O Rajaee, T Musah, N Maghari, S Takeuchi, M Aniya, K Hamashita, ...
IEEE Journal of Solid-State Circuits 45 (4), 719-730, 2010
492010
A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS
T Musah, S Kwon, H Lakdawala, K Soumyanath, UK Moon
2009 IEEE Custom Integrated Circuits Conference, 1-4, 2009
402009
26.4 A 25.6 Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS
TC Hsueh, G Balamurugan, J Jaussi, S Hyvonen, J Kennedy, G Keskin, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
362014
26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS
J Jaussi, G Balamurugan, S Hyvonen, TC Hsueh, T Musah, G Keskin, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
302014
Parallel correlated double sampling technique for pipelined analogue-to-digital converters
T Musah, BR Gregoire, E Naviasky, UK Moon
Electronics Letters 43 (23), 1, 2007
182007
High speed receiver with one-hot decision feedback equalizer
H Venkatram, S Hyvonen, T Musah, BK Casper
US Patent 9,537,682, 2017
172017
A 30% beyond VDD signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp
BR Gregoire, T Musah, N Maghari, S Weaver, UK Moon
IEEE Asian Solid-State Circuits Conference 2011, 345-348, 2011
172011
A 79dB 80 MHz 8X-OSR hybrid delta-sigma/pipeline ADC
O Rajaee, T Musah, S Takeuchi, M Aniya, K Hamashita, P Hanumolu, ...
2009 Symposium on VLSI Circuits, 74-75, 2009
172009
Weak inversion MOS varactors for 0.5 V analog integrated filters
S Chatterjee, T Musah, Y Tsividis, P Kinget
Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005., 272-275, 2005
162005
Digitally trimmable integrated resistors including resistive memory elements
JP Kulkarni, A Ravi, D Somasekhar, G Balamurugan, S Shekhar, T Musah, ...
US Patent 9,589,615, 2017
142017
An interstage correlated double sampling technique for switched-capacitor gain stages
O Rajaee, Y Hu, M Gande, T Musah, UK Moon
2010 IEEE International Symposium on Circuits and Systems (ISCAS), 1252-1255, 2010
72010
Pseudo-differential zero-crossing-based circuit with differential error suppression
T Musah, UK Moon
Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010
72010
Correlated level shifting technique with cross-coupled gain-enhancement capacitors
T Musah, UK Moon
Electronics letters 45 (13), 672, 2009
72009
Robust timing error detection for multilevel baud-rate CDR
T Musah, A Namachivayam
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (10), 3927-3939, 2022
62022
Correlated level shifting integrator with reduced sensitivity to amplifier gain
T Musah, UK Moon
Electronics letters 47 (2), 1, 2011
62011
Time-based error extraction for multilevel receivers
T Musah
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
52020
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