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Sai-Weng Sin (Terry)
Sai-Weng Sin (Terry)
University of Macau
Verified email at um.edu.mo - Homepage
Title
Cited by
Cited by
Year
A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS
Y Zhu, CH Chan, UF Chio, SW Sin, U Seng-Pan, RP Martins, F Maloberti
IEEE Journal of Solid-state circuits 45 (6), 1111-1121, 2010
7432010
A fully integrated digital LDO with coarse–fine-tuning and burst-mode operation
M Huang, Y Lu, SW Sin, U Seng-Pan, RP Martins
IEEE Transactions on Circuits and Systems II: Express Briefs 63 (7), 683-687, 2016
1702016
A wide input range dual-path CMOS rectifier for RF energy harvesting
Y Lu, H Dai, M Huang, MK Law, SW Sin, U Seng-Pan, RP Martins
IEEE Transactions on Circuits and Systems II: Express Briefs 64 (2), 166-170, 2016
1602016
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC
H Wei, CH Chan, UF Chio, SW Sin, RP Martins, F Maloberti
IEEE Journal of Solid-State Circuits 47 (11), 1-1, 2012
1142012
A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS
H Wei, CH Chan, UF Chio, SW Sin, U Seng-Pan, R Martins, F Maloberti
2011 IEEE International Solid-State Circuits Conference, 188-190, 2011
942011
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS
CH Chan, Y Zhu, UF Chio, SW Sin, U Seng-Pan, RP Martins
IEEE Asian Solid-State Circuits Conference 2011, 233-236, 2011
832011
Split-SAR ADCs: Improved linearity with power and speed optimization
Y Zhu, CH Chan, UF Chio, SW Sin, U Seng-Pan, RP Martins, F Maloberti
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (2), 372-383, 2013
822013
A 3.8 mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure
CH Chan, Y Zhu, SW Sin, U Seng-Pan, RP Martins
2012 Symposium on VLSI Circuits (VLSIC), 86-87, 2012
762012
Limit cycle oscillation reduction for digital low dropout regulators
M Huang, Y Lu, SW Sin, U Seng-Pan, RP Martins, WH Ki
IEEE Transactions on Circuits and Systems II: Express Briefs 63 (9), 903-907, 2016
682016
A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC
SS Wong, UF Chio, Y Zhu, SW Sin, U Seng-Pan, RP Martins
IEEE journal of solid-state circuits 48 (8), 1783-1794, 2013
662013
26.5 A 5.5 mW 6b 5GS/S 4ื-lnterleaved 3b/cycle SAR ADC in 65nm CMOS
CH Chan, Y Zhu, SW Sin, U Seng-Pan, RP Martins
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
632015
A 550- W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ADC With 256 Clock Cycles in 65-nm CMOS
B Wang, SW Sin, U Seng-Pan, F Maloberti, RP Martins
IEEE Journal of Solid-State Circuits 54 (4), 1161-1172, 2019
592019
A 1.6-GS/s 12.2-mW seven-/eight-way split time-interleaved SAR ADC achieving 54.2-dB SNDR with digital background timing mismatch calibration
M Guo, J Mao, SW Sin, H Wei, RP Martins
IEEE Journal of Solid-State Circuits 55 (3), 693-705, 2019
582019
Design and experimental verification of a power effective flash-SAR subranging ADC
UF Chio, HG Wei, Y Zhu, SW Sin, U Seng-Pan, RP Martins, F Maloberti
IEEE Transactions on Circuits and Systems II: Express Briefs 57 (8), 607-611, 2010
572010
20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors
Y Lu, J Jiang, WH Ki, CP Yue, SW Sin, U Seng-Pan, RP Martins
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
542015
A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Modulator With Multirate Opamp Sharing
L Qi, SW Sin, U Seng-Pan, F Maloberti, RP Martins
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (10), 2641-2654, 2017
522017
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW multi-bit CT sturdy MASH with DAC non-linearity tolerance
L Qi, A Jain, D Jiang, SW Sin, RP Martins, M Ortmanns
IEEE Journal of Solid-State Circuits 55 (2), 344-355, 2019
472019
A 6 b 5 GS/s 4 interleaved 3 b/cycle SAR ADC
CH Chan, Y Zhu, SW Sin, RP Martins
IEEE Journal of Solid-State Circuits 51 (2), 365-377, 2015
452015
A review and design of the on-chip rectifiers for RF energy harvesting
H Dai, Y Lu, MK Law, SW Sin, U Seng-Pan, RP Martins
2015 IEEE International Wireless Symposium (IWS 2015), 1-4, 2015
452015
A 470-nA quiescent current and 92.7%/94.7% efficiency DCT/PWM control buck converter with seamless mode selection for IoT application
WL Zeng, Y Ren, CS Lam, SW Sin, WK Che, R Ding, RP Martins
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (11), 4085-4098, 2020
402020
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