| An asynchronous and low-power true random number generator using STT-MTJ B Perach IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (11 …, 2019 | 32 | 2019 |
| The bitlet model: A parameterized analytical model to compare PIM and CPU systems R Ronen, A Eliahu, O Leitersdorf, N Peled, K Korgaonkar, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 18 (2), 1-29, 2022 | 25 | 2022 |
| CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM N Talati, H Ha, B Perach, R Ronen, S Kvatinsky IEEE Micro 39 (1), 33-43, 2019 | 22 | 2019 |
| Efficient error-correcting-code mechanism for high-throughput memristive processing-in-memory O Leitersdorf, B Perach, R Ronen, S Kvatinsky 2021 58th ACM/IEEE Design Automation Conference (DAC), 199-204, 2021 | 16 | 2021 |
| SiMT-DSP: A massively multithreaded DSP architecture B Perach, S Weiss IEEE transactions on very large scale integration (VLSI) systems 26 (8 …, 2018 | 9 | 2018 |
| STT-ANGIE: asynchronous true random number generator using STT-MTJ B Perach, S Kvatinsky 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 264-267, 2019 | 8 | 2019 |
| PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics B Perach, R Ronen, B Kimelfeld, S Kvatinsky arXiv 2203, 2022 | 6 | 2022 |
| Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics B Perach, R Ronen, B Kimelfeld, S Kvatinsky IEEE Transactions on Emerging Topics in Computing, 2023 | 4 | 2023 |
| On consistency for bulk-bitwise processing-in-memory B Perach, R Ronen, S Kvatinsky 2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023 | 3 | 2023 |
| ClaPIM: Scalable sequence classification using processing-in-memory M Khalifa, B Hoffer, O Leitersdorf, R Hanhan, B Perach, L Yavits, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023 | 2 | 2023 |
| Training of quantized deep neural networks using a magnetic tunnel junction-based synapse T Greenberg-Toledo, B Perach, I Hubara, D Soudry, S Kvatinsky Semiconductor Science and Technology 36 (11), 114003, 2021 | 2 | 2021 |
| Mtj-based hardware synapse design for quantized deep neural networks TG Toledo, B Perach, D Soudry, S Kvatinsky arXiv preprint, 2019 | 2 | 2019 |
| Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory B Perach, R Ronen, S Kvatinsky 2023 IEEE 36th International System-on-Chip Conference (SOCC), 1-6, 2023 | 1 | 2023 |
| Asynchronous true random number generator using stt-mtj S Kvatinsky, B Perach US Patent App. 17/297,143, 2022 | | 2022 |
| Training of Quantized Deep Neural Networks using a Magnetic Tunnel Junction-Based Synapse TG Toledo, B Perach, I Hubara, D Soudry, S Kvatinsky arXiv preprint arXiv:1912.12636, 2019 | | 2019 |
| MTJ-Based Hardware Synapse Design for Quantized Deep Neural Networks T Greenberg Toledo, B Perach, D Soudry, S Kvatinsky arXiv e-prints, arXiv: 1912.12636, 2019 | | 2019 |
| Design for Test and Hardware Security Utilizing Retention Loss of Memristors..... Y. Gong, F. Qian, and L. Wang 2536 A Chattopadhyay, S Ghosh, W Burleson, D Mukhopadhyay, B Perach, ... | | |
