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Srinidhi Kestur
Srinidhi Kestur
Hardware Engineer at Google
Verified email at google.com
Title
Cited by
Cited by
Year
BLAS Comparison on FPGA, CPU and GPU
S Kestur, JD Davis, O Williams
Proceedings of the 2010 IEEE Annual Symposium on VLSI, 288-293, 2010
2382010
Towards a universal FPGA matrix-vector multiplication architecture
S Kestur, JD Davis, ES Chung
2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012
962012
Universal fpga/asic matrix-vector multiplication architecture
JD Davis, E Chung, S Kestur
US Patent 9,317,482, 2016
622016
A Reconfigurable Accelerator for Neuromorphic Object Recognition
J Sabarad, S Kestur, MS Park, D Dantara, V Narayanan, Y Chen, ...
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific …, 2012
342012
Emulating mammalian vision on reconfigurable hardware
S Kestur, MS Park, J Sabarad, D Dantara, V Narayanan, Y Chen, ...
2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012
332012
Accelerating the Nonuniform fast Fourier transform using FPGAs
S Kestur, S Park, KM Irick, V Narayanan
Field-Programmable Custom Computing Machines (FCCM), 2010 18th IEEE Annual …, 2010
292010
FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for large-sized data
JS Kim, CL Yu, L Deng, S Kestur, V Narayanan, C Chakrabarti
IEEE Workshop on Signal Processing Systems (SiPS 2009), 6, 2009
282009
SHARC: A Streaming Model for FPGA Accelerators and its Application to Saliency
S Kestur, D Dantara, V Narayanan
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, 1-6, 2011
222011
An FPGA-based Accelerator for Cortical Object Classification
MS Park, S Kestur, J Sabarad, V Narayanan, MJ Irwin
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012 …, 2012
172012
An Algorithm-Architecture Co-design Framework for Gridding Reconstruction using FPGAs
S Kestur, K Irick, S Park, A Al Maashri, V Narayanan, C Chakrabarti
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, 585-590, 2011
132011
Accelerators for biologically-inspired attention and recognition
MS Park, C Zhang, M DeBole, S Kestur
Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013
112013
A Scalable Multi-FPGA Framework for Real-time Digital Signal Processing
KM Irick, M DeBole, S Park, A Al Maashri, S Kestur, CL Yu, ...
Proc. of SPIE Vol 7444, 744416-1, 2009
112009
Invited paper: Accelerating Neuromorphic Vision on FPGAs
S Park, S Kestur, KM Irick, V Narayanan
Computer Vision and Pattern Recognition Workshops (CVPRW), 2011 IEEE …, 2011
52011
A streaming FPGA implementation of a steerable filter for real-time applications
S Kestur, D Dantara, V Narayanan
Proceedings of the 19th ACM/SIGDA international symposium on Field …, 2011
52011
Accelerating neuromorphic vision on FPGAs
S Park, S Kestur, KM Irick, V Narayanan
CVPR 2011 WORKSHOPS, 103-108, 2011
22011
An FPGA Drop-In Replacement for Universal matrix-Vector Multiplication
E Chung, JD Davis, S Kestur
2nd Workshop on Intersection of Computer Architecture and Reconfigurable …, 2012
12012
Systems on Reconfigurable Platforms: Design Successes and Challenges
KM Irick, S Kesturvy, A Al Maashri, S Park, V Narayanan
1st Workshop on SoC Architecture, Accelerators and Workloads (SAW-1), 6, 2010
1*2010
Intelligent Vision Systems: Exploring the State-of-the-Art and Opportunities for the Future
S Advani, S Kestur, V Narayanan
2015 IEEE International Symposium on Nanoelectronic and Information Systems …, 2015
2015
Programmable Accelerators for Brain-Inspired Vision
S Kestur, J Sabarad, MS Park, K Irick, V Narayanan
3rd Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW-3), 6, 2012
2012
Technical Program Committee Digital Circuits and FPGA based Design Track
B Joshi, C Jego, C Bobda, D Bol, D Soudris, A Sengupta, H Jiao, H Zheng, ...
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