Bruce Fleischer
Bruce Fleischer
Research Staff Member, IBM T.J. Watson Research Center
Verified email at - Homepage
Cited by
Cited by
Multi-petascale highly efficient parallel supercomputer
S Asaad, RE Bellofatto, MA Blocksome, MA Blumrich, P Boyle, ...
US Patent 9,081,501, 2015
Blue Gene: A vision for protein science using a petaflop supercomputer
F Allen, G Almasi, W Andreoni, D Beece, BJ Berne, A Bright, J Brunheroto, ...
IBM systems journal 40 (2), 310-327, 2001
Active memory cube: A processing-in-memory architecture for exascale systems
R Nair, SF Antao, C Bertolli, P Bose, JR Brunheroto, T Chen, CY Cher, ...
IBM Journal of Research and Development 59 (2/3), 17: 1-17: 14, 2015
A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Training and Inference
B Fleischer, S Shukla, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ...
VLSI Circuits, 2018 Symposium on, C35-C36, 2018
A theoretical study of transducer noise in piezoresistive and capacitive silicon pressure sensors
RR Spender, BM Fleischer, PW Barth, JB Angell
IEEE Transactions on electron devices 35 (8), 1289-1298, 1988
Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros
MP Beakes, BA Chappell, TI Chappell, GS Ditlow, BL Dorfman, ...
US Patent 6,131,182, 2000
The IBM eServer z990 floating-point unit
G Gerwig, H Wetter, EM Schwarz, J Haess, CA Krygowski, BM Fleischer, ...
IBM journal of Research and Development 48 (3.4), 311-322, 2004
Static timing analysis for self resetting circuits
V Narayanan, BA Chappell, BM Fleischer
Proceedings of International Conference on Computer Aided Design, 119-126, 1996
Multi-petascale highly efficient parallel supercomputer
S Asaad, RE Bellofatto, MA Blocksome, MA Blumrich, P Boyle, ...
US Patent 9,971,713, 2018
All-to-all permutation of vector elements based on a permutation pattern encoded in mantissa and exponent bits in a floating-point SIMD architecture
AE Eichenberger, BM Fleischer, MK Gschwind
US Patent 9,652,231, 2017
A 4R2W register file for a 2.3 GHz wire-speed POWER™ processor with double-pumped write operation
GS Ditlow, RK Montoye, SN Storino, SM Dance, S Ehrenreich, ...
2011 IEEE International Solid-State Circuits Conference, 256-258, 2011
4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor
B Curran, B McCredie, L Sigal, E Schwarz, B Fleischer, YH Chan, ...
2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006
A 5GHz+ 128-bit binary floating-point adder for the POWER6 processor
XY Yu, YH Chan, B Curran, E Schwarz, M Kelly, B Fleischer
2006 Proceedings of the 32nd European Solid-State Circuits Conference, 166-169, 2006
Methodology to test pulsed logic circuits in pseudo-static mode
MP Beakes, BA Chappell, TI Chappell, BM Fleischer, RA Haring, ...
US Patent 5,748,012, 1998
Recurrent adrithmetical computation using carry-save arithmetic
RC Agarwal, BM Fleischer, FG Gustavson
US Patent 5,751,619, 1998
Dlfloat: A 16-b floating point format designed for deep learning training and inference
A Agrawal, SM Mueller, BM Fleischer, X Sun, N Wang, J Choi, ...
2019 IEEE 26th Symposium on Computer Arithmetic (ARITH), 92-95, 2019
Low-cost concurrent error detection for floating-point unit (FPU) controllers
M Maniatakos, P Kudva, BM Fleischer, Y Makris
IEEE Transactions on Computers 62 (7), 1376-1388, 2012
Soft error detection for latches
BM Fleischer, MK Gschwind
US Patent 8,188,761, 2012
Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type
AE Eichenberger, BM Fleischer, MK Gschwind
US Patent 7,865,693, 2011
Processor design for extended-precision arithmetic
RF Enenkel, FG Gustavson, BM Fleischer, JE Moreira
US Patent 6,842,765, 2005
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