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Bruce Fleischer
Bruce Fleischer
Research Staff Member, IBM T.J. Watson Research Center
Verified email at us.ibm.com - Homepage
Title
Cited by
Cited by
Year
Multi-petascale highly efficient parallel supercomputer
S Asaad, RE Bellofatto, MA Blocksome, MA Blumrich, P Boyle, ...
US Patent 9,081,501, 2015
5482015
Blue Gene: A vision for protein science using a petaflop supercomputer
F Allen, G Almasi, W Andreoni, D Beece, BJ Berne, A Bright, J Brunheroto, ...
IBM systems journal 40 (2), 310-327, 2001
3512001
Active memory cube: A processing-in-memory architecture for exascale systems
R Nair, SF Antao, C Bertolli, P Bose, JR Brunheroto, T Chen, CY Cher, ...
IBM Journal of Research and Development 59 (2/3), 17: 1-17: 14, 2015
2252015
A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Training and Inference
B Fleischer, S Shukla, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ...
VLSI Circuits, 2018 Symposium on, C35-C36, 2018
1452018
DLFloat: A 16-b floating point format designed for deep learning training and inference
A Agrawal, SM Mueller, BM Fleischer, X Sun, N Wang, J Choi, ...
2019 IEEE 26th Symposium on Computer Arithmetic (ARITH), 92-95, 2019
842019
Multi-petascale highly efficient parallel supercomputer
S Asaad, RE Bellofatto, MA Blocksome, MA Blumrich, P Boyle, ...
US Patent 9,971,713, 2018
732018
9.1 A 7nm 4-core AI chip with 25.6 TFLOPS hybrid FP8 training, 102.4 TOPS INT4 inference and workload-aware throttling
A Agrawal, SK Lee, J Silberman, M Ziegler, M Kang, S Venkataramani, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 144-146, 2021
692021
RaPiD: AI accelerator for ultra-low precision training and inference
S Venkataramani, V Srinivasan, W Wang, S Sen, J Zhang, A Agrawal, ...
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021
642021
A theoretical study of transducer noise in piezoresistive and capacitive silicon pressure sensors
RR Spender, BM Fleischer, PW Barth, JB Angell
IEEE Transactions on electron devices 35 (8), 1289-1298, 1988
641988
Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros
MP Beakes, BA Chappell, TI Chappell, GS Ditlow, BL Dorfman, ...
US Patent 6,131,182, 2000
562000
The IBM eServer z990 floating-point unit
G Gerwig, H Wetter, EM Schwarz, J Haess, CA Krygowski, BM Fleischer, ...
IBM journal of Research and Development 48 (3.4), 311-322, 2004
532004
Static timing analysis for self resetting circuits
V Narayanan, BA Chappell, BM Fleischer
Proceedings of International Conference on Computer Aided Design, 119-126, 1996
521996
Efficient AI system design with cross-layer approximate computing
S Venkataramani, X Sun, N Wang, CY Chen, J Choi, M Kang, A Agarwal, ...
Proceedings of the IEEE 108 (12), 2232-2250, 2020
462020
All-to-all permutation of vector elements based on a permutation pattern encoded in mantissa and exponent bits in a floating-point SIMD architecture
AE Eichenberger, BM Fleischer, MK Gschwind
US Patent 9,652,231, 2017
422017
A 4R2W register file for a 2.3 GHz wire-speed POWER™ processor with double-pumped write operation
GS Ditlow, RK Montoye, SN Storino, SM Dance, S Ehrenreich, ...
2011 IEEE International Solid-State Circuits Conference, 256-258, 2011
402011
A 3.0 TFLOPS 0.62 V scalable processor core for high compute utilization AI training and inference
J Oh, SK Lee, M Kang, M Ziegler, J Silberman, A Agrawal, ...
2020 IEEE Symposium on VLSI Circuits, 1-2, 2020
382020
A scalable multi-TeraOPS core for AI training and inference
S Shukla, B Fleischer, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ...
IEEE Solid-State Circuits Letters 1 (12), 217-220, 2018
332018
Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type
AE Eichenberger, BM Fleischer, MK Gschwind
US Patent 7,865,693, 2011
322011
4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor
B Curran, B McCredie, L Sigal, E Schwarz, B Fleischer, YH Chan, ...
2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006
282006
Methodology to test pulsed logic circuits in pseudo-static mode
MP Beakes, BA Chappell, TI Chappell, BM Fleischer, RA Haring, ...
US Patent 5,748,012, 1998
251998
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