Maksim Jenihhin
Cited by
Cited by
Test time minimization for hybrid BIST of core-based systems
G Jervan, P Eles, Z Peng, R Ubar, M Jenihhin
Journal of Computer Science and Technology 21 (6), 907-912, 2006
Hybrid BIST time minimization for core-based systems with STUMPS architecture
G Jervan, P Eles, Z Peng, R Ubar, M Jenihhin
Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI …, 2003
A scalable model based RTL framework zamiaCAD for static analysis
A Tšepurov, G Bartsch, R Dorsch, M Jenihhin, J Raik, V Tihhomirov
2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012
Code coverage analysis using high-level decision diagrams
J Raik, U Reinsalu, R Ubar, M Jenihhin, P Ellervee
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and …, 2008
Combining dynamic slicing and mutation operators for ESL correction
U Repinski, H Hantson, M Jenihhin, J Raik, R Ubar, G Di Guglielmo, ...
2012 17th IEEE European Test Symposium (ETS), 1-6, 2012
Identification and rejuvenation of nbti-critical logic paths in nanoscale circuits
M Jenihhin, G Squillero, TS Copetti, V Tihhomirov, S Kostin, M Gaudesi, ...
Journal of Electronic Testing 32 (3), 273-289, 2016
Hierarchical identification of NBTI-critical gates in nanoscale logic
S Kostin, J Raik, R Ubar, M Jenihhin, F Vargas, LMB Poehls, TS Copetti
2014 15th Latin American Test Workshop-LATW, 1-6, 2014
Diagnostic modeling of digital systems with multi-level decision diagrams
R Ubar, J Raik, A Jutman, M Jenihhin
Geographic Information Systems: Concepts, Methodologies, Tools, and …, 2013
Mutation analysis for SystemC designs at TLM
V Guarnieri, N Bombieri, G Pravadelli, F Fummi, H Hantson, J Raik, ...
2011 12th Latin American Test Workshop (LATW), 1-6, 2011
Temporally extended high-level decision diagrams for PSL assertions simulation
M Jenihhin, J Raik, A Chepurov, R Ubar
2008 13th European Test Symposium, 61-68, 2008
Mixed hierarchical-functional fault models for targeting sequential cores
J Raik, R Ubar, T Viilukas, M Jenihhin
Journal of Systems Architecture 54 (3-4), 465-477, 2008
Constraint-based test pattern generation at the register-transfer level
T Viilukas, J Raik, M Jenihhin, R Ubar, A Krivenko
13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and …, 2010
High-level decision diagram manipulations for code coverage analysis
K Minakova, U Reinsalu, A Chepurov, J Raik, M Jenihhin, R Ubar, ...
2008 11th International Biennial Baltic Electronics Conference, 207-210, 2008
Assertion checking with PSL and high-level decision diagrams
M Jenihhin, J Raik, A Chepurov, R Ubar
Proc. IEEE Workshop on RTL and High Level Testing, 1-6, 2007
SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic
S Kostin, J Raik, R Ubar, M Jenihhin, T Copetti, F Vargas, LB Poehls
2015 IEEE 18th International Symposium on Design and Diagnostics of …, 2015
EEG analyzer prototype based on FPGA
M Jenihhin, M Gorev, V Pesonen, D Mihhailov, P Ellervee, H Hinrikus, ...
2011 7th International Symposium on Image and Signal Processing and Analysis …, 2011
Hierarchical analysis of short defects between metal lines in CMOS IC
WA Pleskacz, M Jenihhin, J Raik, M Rakowski, R Ubar, W Kuzmicz
2008 11th EUROMICRO Conference on Digital System Design Architectures …, 2008
Qosinnoc: analysis of QoS-aware NoC architectures for mixed-criticality applications
S Avramenko, SP Azad, S Esposito, B Niazmand, M Violante, J Raik, ...
2018 IEEE 21st International Symposium on Design and Diagnostics of …, 2018
Localization of bugs in processor designs using zamiacad framework
A Tepurov, V Tihhomirov, M Jenihhin, J Raik, G Bartsch, JHM Escobar, ...
2012 13th International Workshop on Microprocessor Test and Verification …, 2012
Constraint-based hierarchical untestability identification for synchronous sequential circuits
J Raik, A Rannaste, M Jenihhin, T Viilukas, R Ubar, H Fujiwara
2011 Sixteenth IEEE European Test Symposium, 147-152, 2011
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