Byung Yong Choi
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Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons
JP Llinas, A Fairbrother, G Borin Barin, W Shi, K Lee, S Wu, B Yong Choi, ...
Nature communications 8 (1), 1-6, 2017
Method of fabricating a semiconductor device having self-aligned floating gate and related device
B Choi, C Lee, T Kim, D Park
US Patent 7,329,580, 2008
A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories
KT Park, M Kang, D Kim, SW Hwang, BY Choi, YT Lee, C Kim, K Kim
IEEE Journal of Solid-State Circuits 43 (4), 919-928, 2008
Nonvolatile memory device having multi-bit storage and method of manufacturing the same
B Choi, C Lee, D Park
US Patent 7,511,358, 2009
Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile
DS Woo, JH Lee, WY Choi, BY Choi, YJ Choi, JD Lee, BG Park
IEEE transactions on nanotechnology 1 (4), 233-237, 2002
Methods of manufacturing non-volatile memory devices by implanting metal ions into grain boundaries of variable resistance layers
B Choi, C Lee, KC Park
US Patent 7,883,929, 2011
80nm self-aligned complementary I-MOS using double sidewall spacer and elevated drain structure and its applicability to amplifiers with high linearity
WY Choi, JY Song, BY Choi, JD Lee, YJ Park, BG Park
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure
SK Sung, TY Kim, ES Cho, HJ Cho, BY Choi, CW Oh, BK Cho, CH Lee, ...
IEEE transactions on nanotechnology 5 (3), 174-179, 2006
Methods of reading data from non-volatile semiconductor memory device
A Fayrushin, B Choi
US Patent 7,760,550, 2010
Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions
S Kim, Y Park, W Kim, D Park, E Cho, S Sung, B Choi, T Kim, C Lee
US Patent 7,419,859, 2008
Improving read disturb characteristics by self-boosting read scheme for multilevel NAND Flash memories
M Kang, KT Park, Y Song, S Hwang, BY Choi, Y Song, YT Lee, C Kim
Japanese Journal of Applied Physics 48 (4S), 04C062, 2009
Multi-bit multi-level non-volatile memory device and methods of operating and fabricating the same
B Choi, T Kim, E Cho, S Sung, HJ Cho, D Park, C Lee
US Patent 7,602,010, 2009
Side-gate design optimization of 50 nm MOSFETs with electrically induced source/drain
WY Choi, BY Choi, DS Woo, YJ Choi, JD Lee, BG Park
Japanese journal of applied physics 41 (4S), 2345, 2002
30 nm self-aligned FinFET with large source/drain fan-out structure
DS Woo, BY Choi, WY Choi, MW Lee, JD Lee, BG Park
Electronics Letters 39 (15), 1, 2003
A new 50-nm nMOSFET with side-gates for virtual source-drain extensions
YJ Choi, BY Choi, KR Kim, J duk Lee, BG Park
IEEE Transactions on Electron Devices 49 (10), 1833-1835, 2002
Split gate flash memory device having self-aligned control gate and method of manufacturing the same
B Choi, CW Oh, D Park, D Kim, Y Lee
US Patent 7,341,912, 2008
A new fabrication method for self-aligned nanoscale I-MOS (impact-ionization MOS)
WY Choi, BY Choi, DS Woo, JD Lee, BG Park
Conference Digest [Includes' Late News Papers' volume] Device Research …, 2004
Transistor having gate dielectric layer of partial thickness difference and method of fabricating the same
B Choi, CW Oh, D Park, D Kim
US Patent 7,419,879, 2008
Methods of Manufacturing Non-Volatile Memory Devices
HJ Cho, KC Park, C Lee, B Choi
US Patent App. 11/616,582, 2008
Nonvolatile memory device performing 2-bit operation and method of manufacturing the same
B Choi, B Park, D Park, C Lee
US Patent App. 11/657,133, 2007
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